White Papers
Accelerate Design Closure with Parallel Timing Analysis and Optimization
In response to the trend of ever increasing design sizes and complexity, IC designers have needed more compute power to complete design projects on time. But the growth in computing power is coming from many cores instead of increasing clock speeds, so physical design software must become highly optimized for multicore platforms. In particular, the timing analysis tasks offer the largest single opportunity for reducing design cycle time. Timing analysis is performed throughout the place and route flow. It is the fundamental “cost optimization function” for most routing decisions, and virtually every change in a layout will impact timing in complex ways. So parallelizing timing analysis and optimization can provide the biggest impact on the overall implementation flow. In this paper, we will describe how the Olympus-SoC technology achieves scalable parallelization of timing analysis and optimization throughout the place and route flow. We show example timing analysis runtimes and overall design times on multicore platforms using Olympus-SoC.
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Routing Technology for Advanced-Node IC Designs
As the IC industry accelerates towards the adoption of 32nm and 28nm process nodes, designers face significant new challenges with digital routing. These challenges to sub-nanometer routing—including complex DRC/DFM rules, increasing rule count, very large (1B transistor) designs, and multiple optimization objectives—are stressing the ability of the digital routing engines to meet timing, manufacturability and yield targets. This paper describes the 28 nm routing challenges and presents solutions available from the electronic design automation (EDA) perspective.
Advanced Manufacturing Closure with Calibre® InRoute and Olympus-SoC
Achieving manufacturing signoff is getting more difficult at each node as we encounter significant manufacturing limitations and variability. This paper describes the physical signoff challenges seen in advanced node designs. It then demonstrates how the Calibre InRoute platform provides faster and more reliable DRC/DFM signoff by using the Calibre verification and DFM platform to drive routing and optimization within the Olympus-SoC place and route environment.
Calibre Pattern Matching: Picture It, Match It...Done!
Calibre Pattern Matching is an extension to SVRF that simplifies complex rule checks required for advanced IC processes. This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.
Multi-Voltage Design Flow with Olympus-SoC
In this paper, we will explore the multi-voltage design flow that is currently used in low power IC design, describe the primary challenges of the multi-voltage flow, and discuss the completely automated multi-voltage flow in Mentor Graphics Olympus-SoC place and route system.
Advanced Floorplanning with Olympus-SoC
As the first step in a netlist-to-GDSII design flow, floorplanning presents the SoC designer with challenges and opportunities that affect the rest of the design flow, from block implementation, to chip assembly and top-level closure. It is particularly important in hierarchical floorplanning to quickly solve macro and IO pad placement, accurately estimate timing, power and area, create top-level power networks, and to efficiently partition the design. Floorplanning for large, complex ICs and SoCs depends on a high capacity solution that allows early timing estimations in a multi-mode, multi-corner (MCMM) context, supports all varieties of multi-Vdd flows, and offers wide flexibility between automatic and manual placements of all floorplan objects. In this paper, we review floorplanning challenges and show how the Olympus-SoC implementation system comprehensively addresses all those challenges to produce the best floorplan in the shortest time.
Signal Integrity Optimization with Olympus-SoC
This paper explores the techniques for signal integrity prevention and repair in the Olympus-SoC place and route system. Signal integrity (SI) is a growing problem as higher interconnect density, increasing wire and via resistance, larger variations in resistance, lower threshold voltages, and faster clock speeds conspire to reduce the noise immunity of digital CMOS circuits. Reaching SI closure requires concurrent analysis of timing, power and SI interactions simultaneously across all the different modes and corners, a process referred to as multi-corner, multi-mode (MCMM) optimization.
Low-Power Physical Design with Olympus-SoC
Reducing power consumption has become a key design challenge at 45/32 nm technology nodes. For many designs, optimizing for power is as important as timing, due to the need to reduce package cost and extend battery life. However, the complexities of designing low-power chips can negatively impact performance and time to market. Designers are being forced to juggle macro-level functional complexity issues (multiple operational modes), and micro-level process and manufacturing issues (multiple design corners) that could have conflicting power, timing, signal integrity (SI), manufacturability, and area closure requirements.
In this paper, we will explore techniques currently used in low power IC design, describe the primary challenges of low-power design, and discuss how the Olympus-SoC place and route system implements the optimal low-power solution through all steps of the physical design flow.
Implementation-Quality Prototyping with Olympus-SoC: Accelerating Design Closure for Advanced ICs
The growing complexity of today’s ICs and tight market schedules are driving a demand for more powerful solutions for design prototyping. Prototyping helps designers determine the feasibility of implementing a particular design given the various requirements. By using Olympus-SoC for rapid prototyping early in the design cycle, designers can catch issues with macro placement, missing constraints, RTL problems, and many other design problems. In this paper, we show how design prototyping with the Mentor Graphics Olympus-SoC physical implementation system improves predictability and facilitates design closure.
Confronting Chip Assembly Challenges: Avoid Late-Stage Bottlenecks in Physical Design
The increasing size and complexity of today’s multi-million gate SoCs necessitates hierarchical chip design methodologies, which partition the chip into smaller pieces. A hierarchical methodology is necessary for large SoCs because it extends the capacity of design-automation tools, improves tool runtimes, and limits last minute design changes. However, even hierarchical flows using the current-generation of physical implementation tools are facing problems closing the chip requirement within aggressive schedules. In this paper, we review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.