White Papers
An Optimizer-Assisted Design Methodology For A Two Stage Wideband Feedback Amplifier
With the increasing design complexity and requirements imposed by the various functionalities of modern SoC’s, the analog design process can become a tedious iterative task that may consume a considerable amount of time and effort. In this paper, we present a comprehensive design methodology assisted by an optimization engine where the technique is primarily based upon exploiting the designer’s intuition to guide the optimization flow. The methodology is demonstrated through the design problem of a two stage series-shunt feedback amplifier to be optimized for maximum bandwidth while meeting a set of typical specifications. The methodology deploys Eldo-optimizerTM to demonstrate the flow.
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Behavioral Modeling of the Static Transfer Function of ADCs Using INL Measurements
In this paper, we present a modeling approach for analog-to-digital converters (ADCs) based on modeling the static transfer function using integral nonlinearity (INL) measurements. The methodology relies on applying a Fast Fourier Transform (FFT) test to the output of a real ADC circuit and extracting the significant harmonics. These are used in a behavioral functional model to approximate the INL using a polynomial function. The resulting model is independent of the ADC type or structure, and is suitable for bottom-up system verification. We compare the performance of the new model with other models based on different modeling approaches, and show a gain in simulation speed of up to 300X.
Eldo Premier – High-Performance Hierarchical Analog Simulation
The Eldo Premier simulator addresses the primary concern of analog and mixed-signal designers— performance and capacity increase without sacrificing accuracy. Eldo Premier accelerates the transient simulation, in a spectacular way, of large circuits in either pre-layout or post-layout phases by using sophisticated resolution techniques that do not sacrifice accuracy compared to the golden SPICE results. Eldo Premier accelerates both single-thread simulations and multi-thread simulation. The acceleration of single-thread simulation is provided by new algebraic techniques for the resolution of the system of non-linear differential equations that analog simulators must solve. The acceleration of multi-threaded simulations is a consequence of the natively parallel code of the new simulation kernel and its dedicated data structures. These two acceleration factors naturally combine to offer a significant increase in speed over Eldo Classic. The most significant increases are observed for large circuits (typically at least 10K devices or so), that exhibit some degree of hierarchical regularity. Keywords: Eldo Premier, Fast SPICE, circuit simulation, circuit analysis, parallel processing, speed, capacity, accuracy, foundry certified.
Modeling of Spread-Spectrum Clock Generation System using Simulink
A spread-spectrum phase-locked loop (PLL) clock generation system is modeled and simulated using Simulink. A multi-phase voltage-controlled oscillator (VCO) along with a delta-sigma modulator is used for spreading with a triangular signal of 33 kHz frequency for an output frequency of 3 GHz. The achieved peak power reduction is 16dB at 5000ppm frequency down-spreading. The simulation time is around 4 hours for a complete period of the modulating frequency for a five order of magnitude ratio between the output signal to the modulating one. Keywords: Phase-locked loops (PLLs), spread-spectrum clock generation (SSCG), delta-sigma modulation, multi-phase VCO.
Two-Phase Correlated Level Shifting Switched-Capacitor Techniques
In this paper, two techniques aiming to improve the performance of the switched-capacitor correlated-level-shifting technique are introduced. While boosting the equivalent opamp dc gain, this technique uses three clock phases. First, a time-shifted two-phase sampling approach is introduced with the addition of another set of sampling capacitors. However, this configuration has the disadvantages of error accumulation, increased mismatch and capacitor memory effects. In the second approach, all of these inconveniences are eliminated using a time-aligned two-phase sampling method. Simulation results show the equivalence of a conventional multiply-by-two switched-capacitor stage using a 60-dB dc gain opamp when compared with the correlated-level-shifting, the time-shifted and the time-aligned configurations, all using opamps with only 30-dB dc gain. Keywords: Switched-Capacitor circuits, Opamp gain boosting, Correlated double sampling (CDS), Correlated level shifting (CLS).
A Nonlinear S-parameters Behavioral Model for RF LNAs
A nonlinear behavioral model for radio frequency low noise amplifiers (LNA’s) is presented. The model captures effects of nonlinearity, output power saturation, noise figure and port impedance mismatch. A high-level S-parameters approach is adopted during the model derivation. Consequently, the model inherits the S-parameters dual ability to characterize the transfer function between ports while including their impedances. The model derivation is thoroughly discussed showing how the effects of intermodulation as well as output power saturation can be included within the S-parameters representation for the block. Furthermore, in order to minimize the calibration effort, the model generics are made such that they map directly to typical LNA specifications. It follows that the model as implemented is not topology specific and can be easily calibrated to serve within top-down or bottom-up verification flows. Finally, the model accuracy is validated against reference transistor level simulations. Results comparison shows good agreement is attained. Keywords Behavioral model, intermodulation, LNA, non-linearity, radio-frequency, S parameters.
Characterizing PLL Jitter from Power Supply Fluctuation Using Mixed-Signal
Characterizing PLL Jitter is important yet challenging. Usually done through transistor-level transient analysis, slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (combination of transistor-level blocks and calibrated behavioral models). Among various PLL jitter mechanisms, jitter from CMOS gate switching threshold variation due to power supply fluctuation is chosen to be the focus. Analog/digital converters carrying dynamic power supply dependency, together with behavioral models written in Verilog-AMS, are used to approximately model and characterize the targeted type of jitter. Jitter characterization using this method is applied to two PLL blocks, phase detector and frequency divider. Results show that jitter measured from the proposed method is in good agreement with transistor-level simulation and the speed improvement from mixed-signal simulation is significant, proving this method to be a feasible approach for fast jitter characterization. Keywords PLL jitter, power supply fluctuation, gate switching threshold variation, analog/digital converter, dynamic power supply dependency.
Understanding the Low Power Abstraction
We define four abstract models in common use today for electronic design—electrical, digital gate, digital RTL, and transactional—and discuss the relationships among them. The new low-power model described by IEEE Std 1801-2009 UPF is introduced, and its relationship to the other signal-level models for digital and analog design is defined. We then discuss the connections between the lowpower model and the underlying physical implementation of a chip, elucidating some of the concepts in the low-power model that are missing from the commonly used abstract models. We define extensions to the electrical/RTL boundary model to support application of the low power model in mixed-model simulation. Finally, we recommend extensions to the existing transaction model to reflect the concepts of the low-power model.
ADMS Signals: Nets of User-defined Type in Standard SystemVerilog for Event-driven Analog Modeling
A common requirement in digital-dominated mixed-signal verification is the need for purely event-driven (“real number”, or RN) models that imitate Spice or AMS blocks at low fidelity but high speed. Resolved record types are commonly used for this modeling style in VHDL-based flows. Unfortunately, SystemVerilog defines only one resolved net type, the logic type. A second, non-standard net type, wreal, has been borrowed from Verilog-AMS and, with proprietary extensions, added to some implementations of SystemVerilog. wreal is a single real value with a small, fixed set of resolution functions. It solves only a subset of the problems commonly encountered in event-driven analog modeling.
In contrast, the ADMS_signals approach is completely general and extensible while still conforming strictly to the IEEE SystemVerilog standard. The stored data type can be any type that is legal in SystemVerilog, including arrays and structs (nested to arbitrary depth) and even class instances (objects). The resolution function is a user-supplied SystemVerilog function. Different networks in the same design hierarchy may be given distinct stored type and resolution function.
Efficient Design-Specific Worst-Case Corner Extraction for Integrated Circuits
The circuit example, included in this paper, designed in a commercial CMOS process demonstrates that the proposed SDP formulation can find the worst-case corners both efficiently and robustly, while the traditional QCQP fails to achieve global convergence.
While statistical analysis has been considered as an important tool for nanoscale integrated circuit design, many IC designers would like to know the design-specific worst-case corners for circuit debugging and failure diagnosis. In this paper, we propose a novel algorithm to efficiently extract the worst-case corners for nanoscale ICs. Our proposed approach mathematically formulates a quadratically constrained quadratic programming (QCQP) problem for corner extraction. Next, it applies the Lagrange duality theory to convert the non-convex QCQP problem to a convex semi-definite programming (SDP) problem that is easier to solve. Our circuit example designed in a commercial CMOS process demonstrates that the proposed SDP formulation can find the worst-case corners both efficiently and robustly, while the traditional QCQP fails to achieve global convergence.