White Papers

Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light diraction eects limit the resolution of pattern with ever smaller dimension in ArF lithography using a fixed exposure wave length of 193nm and prevent printing wafer patterns identical to the shapes drawn on the exposure mask. Resolution enhancement techniques such as Optical Proximity Correction (OPC) enable new technologies to be realized in wafer manufacturing. Sub-resolution assist features (SRAF), or scatter bars (SB), provide critical process window enhancements in the lithography process. Traditionally, SRAF generation is based on geometric rules, which are extracted from a large amount of simulation and empirical wafer data from printing test masks.

With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the current process, schematic designers go through extensive simulations to cover all the possible variations of their design parameters and hence of the design functionality. At the same time, layout designers perform time-consuming process-aware simulations (such as lithography simulations) on the full chip layout, which impacts the design turn-around time. In this paper, we present a fast physical layout and electrical-aware Design-For-Manufacturability (DFM) solution that detects hotspot areas in the full chip design without requiring extensive electrical and process simulations. Novel algorithms are proposed to implement the engines that are used to develop this solution. Our proposed flow is examined on a 45 nm industrial Finite Impulse Response (FIR) full chip. The proposed methodology is able to define a list of electrical hotspot devices located on the FIR critical path that experience up to 17% variation in their DC current values due to the effect of process and design context. The total runtime needed to identify and detect these electrical hotspots on the FIR full chip takes nearly 3 minutes, compared to hours when using conventional electrical and process simulations.

In this work, we introduce the use of pattern matching as a potential solution for many verification flows problems. Pattern matching offers a great TAT advantage since it is a DRC based process, thus it is much faster than time consuming LITHO operations. Also, its capability to match geometries directly and operability on many layers simultaneously eliminates complex SVRF coding from our flows. Firstly, we will use the pattern matching in order not to run OPC verification on basic designs identified by the OPC engineer to be error free, which is a very useful technique especially in Memory designs and improves the run time. Then, it will be used to detect waivers, which is hard to code, while running verification flows and eliminate it from the output, and consequently the reviewer will not be distracted by it and concentrate on real errors. And finally, it will be used to detect hot spots in a separate very quick run before standard LITHO verification run which gives the designer/OPC engineer the opportunity to fix design/OPC issues without waiting for lengthy verification flows, and that in turns further improves TAT.

As IC technologies shrink and via defects remain the same size, the probability of via defects increases. Redundant via
insertion is an effective method to reduce yield loss related to via failures, but a large number of extremely complex
design rules make efficient automatic via insertion difficult. This paper introduces an automatic redundant via insertion
flow which is capable of adopting new technologies and complex design rules extremely quickly. Runtime and
efficiency are optimized through a smart insertion scheduling technique. Our experiments show that it efficiently
improves redundant via percentage, making designs more robust against via defects.

Calibre Pattern Matching is an extension to SVRF that simplifies complex rule checks required for advanced IC processes. This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.

As part of the intellectual property (IP) design process, the IP vendor and the foundry negotiate the “waiver” of certain design rule checking (DRC) errors for the process to which the rule deck is targeted. However, when the IP is integrated into a full-chip design, these errors reappear in the full chip DRC results. With no effective way to identify these errors, chip designers must waste time debugging waived and false errors, and repeating the waiver communication process with the foundry. This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results. This new method enables chip designers to eliminate debug time previously spent on these errors, as well as time spent renegotiating waivers with the foundry. Automated waiver management not only helps designers achieve accurate DRC results in a timely and efficient manner, but also reduces time to market by eliminating unnecessary cycles from the verification flow.