White Papers
Analyzing the Device Parasitics Sensitivity and Accuracy of Calibre xACT 3D Field Solver Extraction
As process technologies advance, a parasitic extraction tool requires more sophisticated extraction capability to obtain the effective sensitivity analysis users need, while still meeting schedules and accuracy specifications. Mentor’s new parasitic extraction tool, Calibre® xACT 3D, enabled the Semiconductor Technology Academic Research Center (STARC) to easily and accurately extract the capacitance adjacent to a device on an individual component basis, and create a new reference based on the extraction. With its unique technology and high-quality performance, Calibre xACT 3D can be an integral part of the sophisticated extraction flow needed for today’s complex designs and advanced process technologies.
Describing PERC-based Intent Driven Design
In this paper, we present a fully automated CAD solution that captures the designer’s intent from the schematic netlist, and links these annotations to the proper devices or nets on the physical layout level.
Advanced Memory Cell Characterization with Calibre xACT 3D
Memory designers need to increase bit density to meet exacting specifications for fast data transfer and low power consumption. Higher density increases the interactions between interconnect and devices, yet they have to design with real design margins. Accurate characterization is required at every step of memory design. Memory designers need a tool that can help them analyze parasitic issues accurately and quickly at every stage of the physical design cycle, as well as design cutting-edge memories from basic building blocks to the full chip. Using Calibre xACT 3D at all stages of memory design, from bit cell design to full chip sign-off, ensures a robust design that will work to specification when it is manufactured.
Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs
This paper introduces the first comprehensive and accurate compact resistance-inductance-capacitance-conductance (RLCG) model for through-silicon vias (TSVs) in 3-D ICs valid from low- to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon, the skin effect in TSV metal, and the eddy currents in the silicon substrate. The model is verified against electrostatic measurements as well as a commercial full-wave electromagnetic simulation tool and subsequently employed for various performance (delay) analyses. The compact model is also applicable to TSVs made of carbon nanotube (CNT) bundles, once a slight modification (making the effective conductivity complex) is made. Various geometries (as per the International Technology Roadmap for Semiconductors) and prospective materials (Cu, W, and single-walled/multiwalled CNTs) are evaluated, and a comparative performance analysis is presented. It is shown that CNT-bundle-based TSVs can offer smaller or comparable high-frequency resistance than those of other materials due to the reduced skin effect in CNT bundle structures. On the other hand, the performance (delay) analysis indicates that the performance differences among different TSV materials are rather small. However, it is shown that CNTs provide an improved heat dissipation path due to their much higher thermal conductivity. In addition, the improved mechanical robustness and thermal stability of CNTs also favor their selection as TSV materials in emerging 3-D ICs.
Calibre xACT 3D — No Compromise Extraction For Advanced Transistor Level Design
Calibre® xACT 3D—a new product designed to provide the reference-level accuracy of a 3D field solver coupled with fast performance and high scalability. Calibre xACT 3D leverages its integration into the established best-in-class production design sign-off flow with Calibre LVS and its device and interconnect modeling infrastructure for maximum usability. This paper details how the Calibre xACT 3D extraction solution addresses the extraction challenges for design signoff at advanced nodes.
Layout Pattern Dependence-Aware Highly Accurate Simulation Flow with Calibre nmLVS
In today’s nanometer processes, the “layout pattern dependence” that causes variations in the electrical characteristics due to the shape around MOSFETs is becoming more significant. In response to this, NEC Electronics has introduced a highly accurate design environment that takes layout pattern dependence into consideration. For types of dependence not in the SPICE model, development was carried out to introduce a unique model. For neighboring active-area distance dependence (STI stress), the MIRAI-Selete development model was introduced, and for other types of dependence, independent development was carried out at NEC Electronics. This paper describes the development and calibration of these models that was applied to simulation during design using LVS rules that incorporate shape calculations derived by the ADP extraction feature of the Calibre® nmLVS tool.
An Evolution of Gate and Via Parasitic Resistance Extraction
Cypress has recently modified the parasitic resistance extraction of Vias and Gates. Rather than use a hard number for PEX VIA REDUCTION COUNT for Via grouping, we have found that using FLEXIBLE PEX VIA REDUCTION RESISTANCE for all layers and allowing user specified application of the "STANDARD COUNT" modifier provides nodal reduction and the ability to increase accuracy if needed. For transistor devices, Cypress extracts parasitic resistance to the center of the seed layer, one half the width of gate. Gates only contacted on one side omit one half of the resistance. Experiments have shown that a more accurate estimation is one third. To achieve that accuracy, our flow now uses RESISTANCE DEVICE_SEED to lower poly resistance. Capacitive accuracy is maintained by treating the gate device as poly a equivalent through the use of CAPACITANCE ALIAS. This paper presents details on the evolution of our parasitic resistance flow.
Power of a Platform in the Nanometer Era
Recently, EDA companies have been touting platforms as an answer to the challenges of handing off a design to manufacturing. Certainly as design becomes more complex, process variation becomes more difficult to control, and acceptable cycle time becomes less attainable, the design and manufacturing communities look to EDA for solutions that can help manage outcomes. But what is a platform? And, is it the answer to the problems of the nanometer era?
A New Approach to Sign-Off
Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple design rules. Design rule checking enforced these manufacturing constraints by comparing a characteristic measurement to a threshold value. Layout patterns either passed or failed these checks, with failures being fixed to ensure a DRC-clean sign-off. Then along came nanometer process technology, where increasing rates of silicon failure and longer yield ramps initiated a sea change in how designers deal with process constraints. Designers now find they can no longer adequately describe the effects of process limitations and variations using design rules alone. Most urgently, compliance with design rules no longer always guarantees acceptable yields. Here is why...