White Papers
Addressing Mixed-Signal SoC Physical Design Challenges
Design teams have adopted the mixed signal simulation flow to address the increased demand for mixed mode functionality on a single chip. The physical design environment could benefit from a similar approach to managing two domains in a single environment. Logic driven layout for analog design is becoming more widely adopted and polygon pushing is taking a back seat to parameterized cells and callback functions. There is a great opportunity now to incorporate the tools for managing the mixed language flow into the physical world to provide better design planning and area utilization for IC design.
Using Mentor Graphics Automated Routing Tools in an Analog Layout Flow
Analog layout practices, whether cmos or bipolar, have gone generally unchanged for many years. Now, Mentor Graphics' ICFlow tools including the SDL flow along with the ARoute and IRoute tools enables analog layout designers to better utilize their skills while shifting some of the more mundane layout tasks to the tools. With analog content in ASIC designs increasing and more analog functionality being put into silicon all of the time, the time interval to production is shortening and the need for a more efficient and expedient tool-based solution becomes apparent.
Most analog / mixed signal physical design flows fail to take advantage of current tool suite offerings with respect to automation. Whether due to inexperience or analog design reticence to pursue more modern techniques, today's analog design environment would greatly benefit from even incremental adoption of automation.
This paper describes a methodology for using a mixture of schematic, manually created and assigned layout along with viewpoint properties to allow the IRoute and ARoute tools to perform in a more analog-friendly mode. The mixture of techniques described can be implemented in whole as part of a comprehensive SDL / ECO analog design and layout flow, or more likely in piecemeal fashion as part of an incremental technique adoption.
ST Microelectronics design platform for micro and nano technologies based on Mentor Graphics IC Flow
This design platform allows access to the world leading ST Microelectronics CMOS, BiCMOS and IPAD technologies, with IC/IPAD co-design facility for system in package integration. It supports Mentor Graphics proven mixed-signal design and layout tools (Design Architect-IC, IC Station), mixed-signal design analysis tools (AdvanceMS, Eldo, Eldo RF), and Mentor Graphics verification tools (Calibre)
Designing an RF System-In-Package with Improved IC Design Environment
The complete ST SIP RF platform provides a full design environment with several different ST technologies: IC, IPAD(tm), external filters, Surface Mounted Technologies (SMT), and passives embedded in laminate (BGA). ST is facing these design challenges in the package for RF: expertise on new technologies (several layers, routing, embedded passives), assembly rules and model library for SMT, assembly rules for dice stacking, design rules and model library for embedded passives, IC / IPAD(tm) wire bonding and flipchip compatibility. Before developing a complete RF design environment for this new technology, it is necessary to answer a few questions. Who should be the SIP designer? Should it be a package designer who knows all package constraints or should it be a RF designer who knows the constraints of his design.
Which tools should we use? A specific SIP tool which enables us to design very complex packages and which addresses all SIP constraints or Mentor Graphics IC Flow tool suite, which is well known by the RF designer, but was not designed for SIP design?
When the tools are chosen, do they address all SIP and RF constraints or should they be enhanced? This paper will describe the choices that were made at ST to answer these questions in order to reach a complete production RF SIP flow.
A Fully Automated Approach for Analog Circuit Reuse
Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It is not based on any optimization techniques, but rather relies on a new algorithm based on knowledge extraction, which makes it a very fast technique. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then produces a re-sized design in the target technology with the same performance as the original design. The migration of a low voltage Delta Sigma modulator is presented in this paper to validate the migration engine.
Bluetooth Transceiver Design: A Top-Down Flow for Complex RF Mixed-Signal ICs
This paper describes the design challenges of BlueTraCTM, a low-cost, low-power radio transceiver. It details how a topdown methodology along with mixed-signal/mixed-mode techniques and behavioral modeling can be used to effectively address and solve the design challenges of this complex RF mixed-signal IC. The methodology leverages an out-of-the-box design flow from Mentor Graphics that includes Design Architect-IC for design entry and simulation control, Questa ADMS for single-kernel mixed-mode simulation, IC Station for schematic-driven physical layout, and Calibre for physical verification and extraction.
Addressing the Layout Challenges of Increasing Analog Content in SoCs
The growing complexity and functionality of SoC designs is increasing the quantity of analog blocks on SoC chips. End user applications, including video cell phones, MP3 music devices and more complex wireless devices such as web browsers and PDAs are demanding broader functionality on single devices. This demand for increasingly diverse capabilities on a single device, combined with the drive for longer battery life, lower power consumption and smaller sizes has driven the development of mixed-signal devices on a single chip.
By 2006 it is estimated that 75% of all SoC designs will contain some analog blocks. This demand is forcing design teams, both digital and analog, to incorporate foreign blocks into their design. The methodology for planning, implementing and assembling digital blocks is well-defined and understood. In cases where the digital component comprises the majority of the design, analog blocks are generally included as abstractions and handled as black boxes, isolated from the rest of the layout.
Bluetooth Transceiver Design with VHDL-AMS
This paper describes the design challenges of BlueTraC, a low-cost, low-power radio transceiver and the usage of mixed-signal/mixed-mode techniques and behavioral modeling with Questa ADMS from Mentor Graphics to address and solve them. BlueTraC from Spirea is a Bluetooth 1.1 compliant Class 2 radio transceiver. In addition to all the required RF and analog functions, the chip also includes a complete digital GFSK modem, making it a very complex mixed-signal (MS) system-on-chip (SoC). VHDL-AMS, the mixed-signal IEEE 1076.1 standard modeling language, was used to describe the SoC building blocks at different levels of detail and complexity. This permitted us to perform top level functional verification and debugging, as well as detailed subsystem simulations throughout the design process. We are presenting the concept and the results we obtained, in terms of performance and accuracy. The methodology that we deployed increased the confidence in silicon success and allowed on time delivery.