White Papers
Developing a Complete Critical Feature Analysis Solution—Part 3: Parameter Weightings for CFA Metrics
Critical Feature Analysis (CFA) is a data analysis solution for understanding the impact and priority of recommended rule compliance issues in a design. CFA is one part of a comprehensive design for manufacturing (DFM) design flow. This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.
Part 3 explains various techniques and approaches used to calculate CFA weightings, and provides examples of weighting calculations.
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Modern IC Packaging
Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies.
Ready for 3D-IC
This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers.
3D-IC System Verification Methodology: Solutions and Challenges
Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction. Discusses new challenges and EDA tools to responds to those challenges. An example illustrates a true 3D-IC stack verification using a GDS based flow.
Analyzing the Device Parasitics Sensitivity and Accuracy of Calibre xACT 3D Field Solver Extraction
As process technologies advance, a parasitic extraction tool requires more sophisticated extraction capability to obtain the effective sensitivity analysis users need, while still meeting schedules and accuracy specifications. Mentor’s new parasitic extraction tool, Calibre® xACT 3D, enabled the Semiconductor Technology Academic Research Center (STARC) to easily and accurately extract the capacitance adjacent to a device on an individual component basis, and create a new reference based on the extraction. With its unique technology and high-quality performance, Calibre xACT 3D can be an integral part of the sophisticated extraction flow needed for today’s complex designs and advanced process technologies.
Describing PERC-based Intent Driven Design
In this paper, we present a fully automated CAD solution that captures the designer’s intent from the schematic netlist, and links these annotations to the proper devices or nets on the physical layout level.
How to Reduce the Need for Guardbanding a Flash ADC Design
For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction is critical for first silicon success. New 3D parasitic extraction technology applied to a flash ADC circuit design reduces the need for extra guardbanding and ensures that it will work according to the specifications when manufactured.
Advanced Memory Cell Characterization with Calibre xACT 3D
Memory designers need to increase bit density to meet exacting specifications for fast data transfer and low power consumption. Higher density increases the interactions between interconnect and devices, yet they have to design with real design margins. Accurate characterization is required at every step of memory design. Memory designers need a tool that can help them analyze parasitic issues accurately and quickly at every stage of the physical design cycle, as well as design cutting-edge memories from basic building blocks to the full chip. Using Calibre xACT 3D at all stages of memory design, from bit cell design to full chip sign-off, ensures a robust design that will work to specification when it is manufactured.
Routing Technology for Advanced-Node IC Designs
As the IC industry accelerates towards the adoption of 32nm and 28nm process nodes, designers face significant new challenges with digital routing. These challenges to sub-nanometer routing—including complex DRC/DFM rules, increasing rule count, very large (1B transistor) designs, and multiple optimization objectives—are stressing the ability of the digital routing engines to meet timing, manufacturability and yield targets. This paper describes the 28 nm routing challenges and presents solutions available from the electronic design automation (EDA) perspective.
Behavioral Modeling of the Static Transfer Function of ADCs Using INL Measurements
In this paper, we present a modeling approach for analog-to-digital converters (ADCs) based on modeling the static transfer function using integral nonlinearity (INL) measurements. The methodology relies on applying a Fast Fourier Transform (FFT) test to the output of a real ADC circuit and extracting the significant harmonics. These are used in a behavioral functional model to approximate the INL using a polynomial function. The resulting model is independent of the ADC type or structure, and is suitable for bottom-up system verification. We compare the performance of the new model with other models based on different modeling approaches, and show a gain in simulation speed of up to 300X.