White Papers

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies.

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers.

As process technologies advance, a parasitic extraction tool requires more sophisticated extraction capability to obtain the effective sensitivity analysis users need, while still meeting schedules and accuracy specifications. Mentor’s new parasitic extraction tool, Calibre® xACT 3D, enabled the Semiconductor Technology Academic Research Center (STARC) to easily and accurately extract the capacitance adjacent to a device on an individual component basis, and create a new reference based on the extraction. With its unique technology and high-quality performance, Calibre xACT 3D can be an integral part of the sophisticated extraction flow needed for today’s complex designs and advanced process technologies.

In this paper, we present a fully automated CAD solution that captures the designer’s intent from the schematic netlist, and links these annotations to the proper devices or nets on the physical layout level.

Memory designers need to increase bit density to meet exacting specifications for fast data transfer and low power consumption. Higher density increases the interactions between interconnect and devices, yet they have to design with real design margins. Accurate characterization is required at every step of memory design. Memory designers need a tool that can help them analyze parasitic issues accurately and quickly at every stage of the physical design cycle, as well as design cutting-edge memories from basic building blocks to the full chip. Using Calibre xACT 3D at all stages of memory design, from bit cell design to full chip sign-off, ensures a robust design that will work to specification when it is manufactured.

As the IC industry accelerates towards the adoption of 32nm and 28nm process nodes, designers face significant new challenges with digital routing. These challenges to sub-nanometer routing—including complex DRC/DFM rules, increasing rule count, very large (1B transistor) designs, and multiple optimization objectives—are stressing the ability of the digital routing engines to meet timing, manufacturability and yield targets. This paper describes the 28 nm routing challenges and presents solutions available from the electronic design automation (EDA) perspective.