Technical Papers
Reducing Physical Verification Cycle Time
As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.
Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.
Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.
Reducing IC Cycle Time with Calibre
Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physical verification should take longer and why we should be given more time than we had for our previous project. As nice as that would be, this is not the case. Increasing competitive environments and the always present compulsion to get products out to market in a timely manner have not permitted such luxuries. Fortunately, despite conspiring forces to elongate this already difficult task, there is a light at the end of the tunnel (no, not a train coming the other direction), the Calibre suite of verification tools, specifically Calibre nmDRC, Calibre nmLVS and Calibre Incremental DRC.
Setting MRC Rules: Balancing Inspection Capabilities, Defect Sensitivity and OPC
One of the challenges associated with shrinking design dimensions is finding photomask inspection settings which achieve sufficient defect detection capabilities while supporting aggressive Optical Proximity Correction (OPC). The most recent technology nodes require very aggressive and advanced Resolution Enhancement Techniques (RETs) which involve printing small features that are challenging for mask inspection tools. We examine the problems associated with constraining Models-Based OPC with mask inspection driven rules. We give examples of a 45nm technology node contact layer design which will receive sub-optimal OPC treatment due to mask inspection constraints. We then take the mask defect specification typically used for this mask layer, and use Monte Carlo simulation methods to place minimum sized simulated defects in various locations in close proximity to these sensitive layouts.
Simulations of the optimal OPC are compared to optimal OPC with defects, and to the sub-optimal constrained OPC. Using knowledge about the frequency of small defects on masks, one can compare the risks associated with small mask defects to the risks associated with sub-optimal OPC. This exercise demonstrates that there are some instances where mask rules based on inspection capabilities and defect sensitivity alone can be problematic, and that OPC requirements need to be taken into account when choosing a defect specification and an inspection strategy. We conclude by proposing a strategy for balancing these requirements in a practical manner.
Implementation of Adaptive Site Optimization in Model-Based OPC for Minimizing Ripples
The OPC treatment of aerial mage ripples (local variations in aerial contour relative to constant target edges) is one of the growing issues with very low-k1 lithography employing hard off-axis illumination. The maxima and minima points in the aerial image, if not optimally treated within the existing model based OPC methodologies, could induce severe necking or bridging in the printed layout.
The current fragmentation schemes and the subsequent site simulations are rule-based, and hence not optimized according to the aerial image profile at key points. The authors are primarily exploring more automated software methods to detect the location of the ripple peaks as well as implementing a simplified implementation strategy that is less costly. We define this to be an adaptive site placement methodology based on aerial image ripples.
Recently, the phenomenon of aerial image ripples was considered within the analysis of the lithography process for cutting-edge technologies such as chromeless phase shifting masks and strong off-axis illumination approaches. Effort is spent during the process development of conventional model-based OPC with the mere goal of locating these troublesome points. This process leads to longer development cycles and so far only partial success was reported in suppressing them (the causality of ripple occurrence has not yet fully been explored). We present here our success in the implementation of a more flexible model-based OPC solution that will dynamically locate these ripples based on the local aerial image profile nearby the features edges. This model-based dynamic tracking of ripples will cut down some time in the OPC code development phase and avoid specifying some rule-based recipes.
Our implementation will include classification of the ripples bumps within one edge and the allocation of different weights in the OPC solution. This results in a new strategy of adapting site locations and OPC shifts of edge fragments to avoid any aggressive correction that may lead to increasing the ripples or propagating them to a new location. More advanced adaptation will be the ripples-aware fragmentation as a second control knob, beside the automated site placement.
Tolerable CD Variation Analyzer Using Perturbed Nominal Models Demonstrated on altPSM
At the 65 nm node and beyond, printing the dense and isolated pitches as well as the 2D patterns within tight tolerance across the full range of known process conditions becomes a major challenge, and even more critical in the context of double exposure masks. Post-OPC simulation at nominal conditions is not sufficient to accurately assess and disposition severe errors and monitor residual proximity effects and their implications such as channel length variation. In this paper, we explore a methodology that adopts multiple simulations to model the variability in the lithography process. This approach is predicting the process behavior by the modulation of the related lithography parameters, such as: dose, focus, and overlay. The goal is to identify the unacceptable deviation of the printed image from the designed target due to process variations. The method also provides a better statistical evaluation of the quality and robustness of the implemented Resolution Enhancement Techniques (RET) & Design for Manufacturability (DfM) solution.
Optimization of OPC Runtime Using Efficient Optical Simulation
Model-Based Optical Proximity Correction (MBOPC) is now found in nearly all resolution enhancement recipes used in leading technology integrated circuit fabrication facilities. Many masks now have critical dimensions less than the exposure wavelength, which results in light diffraction that distorts the image projected onto the wafer. The industry is relying more and more on MBOPC to compensate for optical effects that are induced during the exposure of these masks. The MBOPC operation is usually the highest computational time contributor in the RET flow. MBOPC procedures include the fragmentation of layout edges longer than a specific value into a number of subedges(fragments).
The software engine can move and manipulate each fragment to improve the image transferred to the wafer. In the sparse MBOPC approach, each fragment receives one or more optical simulation sites, which is a one-dimensional array of points where light intensity is sampled and calculated. To correctly capture the resist behavior at each simulation site, there must be enough points to ensure extension of the site to a certain distance from the fragment. Adding more points beyond this distance does not add any benefit, but can significantly increase the runtime.
This paper presents an automated method that analyzes layouts for different technology nodes that depend on sparse simulations as their MBOPC engine, and reports the optimized number of simulation points that need to be in the
simulation site to get the desired accuracy and optimum runtime performance.
Safe Interpolation Distance for VT5 Resist Model
As the technology shrinks toward 65nm technology and beyond, Optical Proximity Correction (OPC) becomes more important to insure proper printability of high-performance integrated circuits. This correction involves some geometrical modifications to the mask polygons to account for light diffraction and etch biasing. Model-based OPC has proven to be a convenient, accurate, and efficient methodology. In this method, raw calibration data are measured from the process. These data are used to build a VT5 resist model [1] that accounts for all proximity effects that attendant to the lithography process. To ensure the reliability of the calibrated VT5 model, these data must be broad in the image parameter space (IPS) to account for different one-dimensional and two-dimensional features for the design intent. Failure to provide sufficient IPS (i.e. mimic the design intent) coverage during model calibration could result in marginalizing the VT5 model during OPC, but is difficult to judge when there is enough data volume to safely interpolate and extrapolate design intent. In this paper we introduce a new metric called Safe Interpolation Distance(SID). This metric is a multi-dimensional metric which can be used to automatically detect the portions of the target design that are not covered well by the desired VT5 model.
Addressing Reliability and Circuit Verification Challenges with CalibreĀ® PERC
Circuit design implementation has become progressively complex in deep submicron technologies. Multiple processor cores, I/Os, several types of memories, complex analog circuits, and synthesized logic are being designed onto the same chip. Advanced IP integration proficiency strategies are needed to realize today’s complex systems-on-chip (SoC) designs, not to mention the high demand in the communications semiconductor market.
Ensuring product reliability to meeting all design goals while achieving good yield is a significant and growing challenge. Today, designers need physical verification tools with greater flexibility and the power to handle emerging circuit verification demands, such as the ability to deal with more complex design rules, multiple voltage domains, and advanced device parameters.
Simultaneous Model-based Main Feature and SRAF Optimization for 2D SRAF Implementation to 32 nm Critical Layers
Sub-resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for the optimum placement of 2D SRAF structures using state of the art Calibre RET flow. In this approach, the optimal SRAF shapes are achieved simultaneously during the OPC step. The SRAF and main features are optimized to account for their edge placement and process window metrics (aerial image slope/contrast, out of focus/dose EPE, etc…). The resulting mask shapes deliver some of the properties that can be obtained using the Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost no impact on the runtime. The implemented model-based optimization flow remains compatible with the current OPC production flows.
Automatic Assist Feature Placement Optimization Based on Process-Variability Reduction
To maximize the process window and CD control of main features, sizing and placement rules for sub-resolution assist features (SRAF) need to be optimized, subject to the constraint that the SRAFs not print through the process window. With continuously shrinking target dimensions, generation of traditional rule-based SRAFs is becoming an expensive process in terms of time, cost and complexity. This has created an interest in other rule optimization methodologies, such as image contrast and other edge- and image-based objective functions. In this paper, we propose using an automated model-based flow to obtain the optimal SRAF insertion rules for a design and reduce the time and effort required to define the best rules. In this automated flow, SRAF placement is optimized by iteratively generating the space-width rules and assessing their performance against process variability metrics. Multiple metrics are used in the flow. Process variability (PV) band thickness is a good indicator of the process window enhancement. Depth of focus (DOF), the total range of focus that can be tolerated, is also a highly descriptive metric for the effectiveness of the sizing and placement rules generated. Finally, scatter bar (SB) printing margin calculations assess the allowed exposure range that prevents scatter bars from printing on the wafer.
Subsystem Exchange in a Concurrent Design Process Environment
This paper provides insight into the novel solutions used to build SoCs targeting increased productivity in a complex environment. Design of such SoCs relies on multi-team, multi-site cooperation and data exchange. The data exchange, made possible though descriptions based on The SPIRIT Consortium’s IP-XACT™ specification and the automation for its processing, forms the basis of the approach. Initially, the specification focused at IP reuse; this has now been extended to SoC subsystem exchange. This paper also describes state-of-the-art subsystem design automation and improvement opportunities, based on a close collaboration between NXP Semiconductors and Mentor Graphics. We do not cover all the aspects of reuse but mainly stress the concurrent engineering process.
