Technical Papers
Reducing Physical Verification Cycle Time
Sign-off for IC tape-out has undergone dramatic changes over the past several years. The size and complexity of nanometer IC design and the volume of geometric content for related layouts all skyrocketed. Additionally, extensive changes occurred in the processing requirements for nanometer design processes. Physical impacts that we once could ignore now have measurable electrical effects.
As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.
Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.
Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.
Variability Aware Modeling and Characterization in Standard Cell in 45 nm CMOS with Stress Enhancement Technique
Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of 2.8% to +3.6% and Idsat change of 10% to +14% are removed from uncertain margin in 45 nm corner libraries.
Layout Pattern Dependence-Aware Highly Accurate Simulation Flow with Calibre nmLVS
In today’s nanometer processes, the “layout pattern dependence” that causes variations in the electrical characteristics due to the shape around MOSFETs is becoming more significant. In response to this, NEC Electronics has introduced a highly accurate design environment that takes layout pattern dependence into consideration. For types of dependence not in the SPICE model, development was carried out to introduce a unique model. For neighboring active-area distance dependence (STI stress), the MIRAI-Selete development model was introduced, and for other types of dependence, independent development was carried out at NEC Electronics. This paper describes the development and calibration of these models that was applied to simulation during design using LVS rules that incorporate shape calculations derived by the ADP extraction feature of the Calibre® nmLVS tool.
Chip-Scale Copper Electroplating and CMP Simulator
Mentor Graphics has developed a chip-scale copper electroplating and chemical-mechanical polishing simulator called CMP Optimize. CMP Optimize is part of the Calibre® WORKBench™ platform, and is intended for use with various Design for Manufacturing applications, such as SmartFill optimizations, accurate parasitic extractions, and depth-of-focus variability compensations. CMP Optimize is tightly integrated with Mentor Graphics’ Calibre product line, which provides planarity hotspot detection, as well as thickness analysis and optimization. CMP Optimize is currently the only solution in the industry that gives designers the ability to build models for copper metallization processes. Much like models for lithography, the customer’s process or foundry team builds and owns the copper models. This white paper introduces the CMP Optimize tool from a model-building perspective. It discusses the necessary inputs, model-building methodology from a calibration and optimization standpoint, output data analysis, and model validation capabilities.
Signal Integrity Optimization with Olympus-SoC
This paper explores the techniques for signal integrity prevention and repair in the Olympus-SoC place and route system. Signal integrity (SI) is a growing problem as higher interconnect density, increasing wire and via resistance, larger variations in resistance, lower threshold voltages, and faster clock speeds conspire to reduce the noise immunity of digital CMOS circuits. Reaching SI closure requires concurrent analysis of timing, power and SI interactions simultaneously across all the different modes and corners, a process referred to as multi-corner, multi-mode (MCMM) optimization.
Equation-Based DRC: A Novel Approach to Resolving Complex Nanometer Design Issues
Traditional physical verification uses single-dimensional design rule checks (DRC) to identify sensitive layout features likely to fail during manufacturing. Checks that require coding large tables of measurement thresholds are extremely difficult to implement using traditional DRC approaches. A new technique, known as Equation-Based DRC (eqDRC), extends traditional DRC to define grouped multi-dimensional feature measurements using flexible mathematical expressions, providing a customizable physical modeling tool and enabling the analysis of complex interactions that could not previously be verified. This paper will examine the implementation and demonstrate the benefits of eqDRC through a variety of examples comparing traditional DRC with eqDRC approaches.
A Case Study: Critical Area and Critical Feature Analysis of Production 90nm Designs at LSI Corporation
This paper documents the results of a critical area and critical feature analysis study of four LSI production 90 nm designs. The recommended rule adherence and statistical sensitivity to random particle defects were evaluated and used to prioritize the yield issues of IP, memories and routing within the various products. Automated correction of recommended rule violations was run in the logic routing to quantify the amount of optimization possible without re-routing the chips. Comparisons were done between the chips to identify commonalities and differences in different design implementations
Accelerate Design Closure with Parallel Timing Analysis and Optimization
In response to the trend of ever increasing design sizes and complexity, IC designers have needed more compute power to complete design projects on time. But the growth in computing power is coming from many cores instead of increasing clock speeds, so physical design software must become highly optimized for multicore platforms. In particular, the timing analysis tasks offer the largest single opportunity for reducing design cycle time. Timing analysis is performed throughout the place and route flow. It is the fundamental “cost optimization function” for most routing decisions, and virtually every change in a layout will impact timing in complex ways. So parallelizing timing analysis and optimization can provide the biggest impact on the overall implementation flow. In this paper, we will describe how the Olympus-SoC technology achieves scalable parallelization of timing analysis and optimization throughout the place and route flow. We show example timing analysis runtimes and overall design times on multicore platforms using Olympus-SoC.
Low-Power Physical Design with Olympus-SoC
Reducing power consumption has become a key design challenge at 45/32 nm technology nodes. For many designs, optimizing for power is as important as timing, due to the need to reduce package cost and extend battery life. However, the complexities of designing low-power chips can negatively impact performance and time to market. Designers are being forced to juggle macro-level functional complexity issues (multiple operational modes), and micro-level process and manufacturing issues (multiple design corners) that could have conflicting power, timing, signal integrity (SI), manufacturability, and area closure requirements.
In this paper, we will explore techniques currently used in low power IC design, describe the primary challenges of low-power design, and discuss how the Olympus-SoC place and route system implements the optimal low-power solution through all steps of the physical design flow.
DFM-Compliant IP: Why You Need It, How You Get It
Customers want their designs to have the best yields from the foundry. When those designs include external IP, customers expect and demand that the IP has been optimized with the latest Design For Manufacturing (DFM) technologies to minimize variability and ensure manufacturability. IP vendors must collaborate with the foundries and EDA companies to ensure IP DFM compliance and optimization. This paper examines the components of an IP DFM solution, and the process by which the foundry, IP vendor and EDA company have worked together to implement and ensure successful DFM compliance for IP.
Your Fill Solution Should Match Your Fill Analysis
Fill solutions become more challenging at each smaller node because manufacturing processes and physical interactions become more sensitive to small metal density variations. In addition, the performance of the chip becomes more sensitive to parasitic capacitance (which is increased by adding metal fill) and variations in interconnect resistance (due to CMP impact on metal thickness). Meeting all of these constraints requires better analysis to predict the manufacturing and electrical impacts of fill, and more sophisticated algorithms that optimize the use of metal fill features to solve the three fundamental fill issues. This paper defines the requirements and goals of any fill solution, examines the technology behind Mentor’s four fill solutions, and explains how each can be used to satisfy fill requirements, depending on the needs of the design.