Technical Papers
Reducing Physical Verification Cycle Time
Sign-off for IC tape-out has undergone dramatic changes over the past several years. The size and complexity of nanometer IC design and the volume of geometric content for related layouts all skyrocketed. Additionally, extensive changes occurred in the processing requirements for nanometer design processes. Physical impacts that we once could ignore now have measurable electrical effects.
As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.
Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.
Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.
Variability Aware Modeling and Characterization in Standard Cell in 45 nm CMOS with Stress Enhancement Technique
Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of 2.8% to +3.6% and Idsat change of 10% to +14% are removed from uncertain margin in 45 nm corner libraries.
Advanced Floorplanning with Olympus-SoC
As the first step in a netlist-to-GDSII design flow, floorplanning presents the SoC designer with challenges and opportunities that affect the rest of the design flow, from block implementation, to chip assembly and top-level closure. It is particularly important in hierarchical floorplanning to quickly solve macro and IO pad placement, accurately estimate timing, power and area, create top-level power networks, and to efficiently partition the design. Floorplanning for large, complex ICs and SoCs depends on a high capacity solution that allows early timing estimations in a multi-mode, multi-corner (MCMM) context, supports all varieties of multi-Vdd flows, and offers wide flexibility between automatic and manual placements of all floorplan objects. In this paper, we review floorplanning challenges and show how the Olympus-SoC implementation system comprehensively addresses all those challenges to produce the best floorplan in the shortest time.
Automated DRC Waiver Management (or, How I Learned to Stop Worrying About IP Waivers and Love Calibre Auto-Waiver)
This paper explains the Calibre Auto-Waiver product, and discusses how the auto-waiver process significantly reduces the time and risks associated with implementing third-party IP.
Integration of third-party intellectual property (IP) into integrated circuit (IC) designs has always been a potential time trap for IC designers. IP design rule violations that were waived by the foundry show up during IC verification without any indication as to their waived status. The IC designer has no choice but to analyze and resolve these errors just like any other, wasting significant manhours and cycle time. Calibre Auto-Waiver, Calibre nmDRC’s automated waiver management capability, provides IP designers with automated identification of design rule violations granted waiver status during IP development. During integration of the IP into larger designs, IC designers can use Calibre Auto-Waiver to recognize and remove these errors during design rule checking (DRC), avoiding the need to analyze and debug waived errors. In addition, Calibre Auto-Waiver identifies any waived errors that fall into “marginal” waiver status, allowing the IC designer to investigate these errors as needed to ensure manufacturability. After DRC is complete, Calibre Auto-Waiver enables the designer to quickly review the waiver status of all IP errors, as final assurance that no IP error has been overlooked.
Developing a Complete Critical Feature Analysis Solution—Part 5: Generating Benchmark CFA Data
Critical Feature Analysis (CFA) is a data analysis solution for understanding the impact and priority of recommended rule compliance issues in a design. CFA is one part of a comprehensive design for manufacturing (DFM) design flow. This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.
Part 5 provides guidance on establishing and maintaining benchmark metrics to ensure CFA data reflects production values.
Developing a Complete Critical Feature Analysis Solution—Part 4: Recommended Rule Weighting
Critical Feature Analysis (CFA) is a data analysis solution for understanding the impact and priority of recommended rule compliance issues in a design. CFA is one part of a comprehensive design for manufacturing (DFM) design flow. This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.
Part 4 demonstrates a general methodology that can be used to characterize the proper weighting of a recommended rule.
Developing a Complete Critical Feature Analysis Solution—Part 3: Parameter Weightings for CFA Metrics
Critical Feature Analysis (CFA) is a data analysis solution for understanding the impact and priority of recommended rule compliance issues in a design. CFA is one part of a comprehensive design for manufacturing (DFM) design flow. This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.
Part 3 explains various techniques and approaches used to calculate CFA weightings, and provides examples of weighting calculations.
Developing a Complete Critical Feature Analysis Solution—Part 2: Defining CFA Metrics
Critical Feature Analysis (CFA) is a data analysis solution for understanding the impact and priority of recommended rule compliance issues in a design. CFA is one part of a comprehensive design for manufacturing (DFM) design flow. This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.
Part 2 explains how metrics are defined to enable CFA to evaluate and prioritize recommended rule compliance.
Developing a Complete Critical Feature Analysis Solution—Part 1: What Is CFA and Why Do I Need It?
Critical Feature Analysis (CFA) is a data analysis solution for understanding the impact and priority of recommended rule compliance issues in a design. CFA is one part of a comprehensive design for manufacturing (DFM) design flow. This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability. Part 1 explains the use of recommended rules and introduces the basic concepts of CFA.
Automated DRC Violation Waiver Management for IP Block Integration
As part of the intellectual property (IP) design process, the IP vendor and the foundry negotiate the “waiver” of certain design rule checking (DRC) errors for the process to which the rule deck is targeted. However, when the IP is integrated into a full-chip design, these errors reappear in the full chip DRC results. With no effective way to identify these errors, chip designers must waste time debugging waived and false errors, and repeating the waiver communication process with the foundry. This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results. This new method enables chip designers to eliminate debug time previously spent on these errors, as well as time spent renegotiating waivers with the foundry. Automated waiver management not only helps designers achieve accurate DRC results in a timely and efficient manner, but also reduces time to market by eliminating unnecessary cycles from the verification flow.
Restrictive Design Rules and Their Impact on 22 nm Design and Physical Verification
Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, and thus impacts both performance and yield of advanced node chips. To ensure the manufacturability and performance of chips at 22 nm, one approach the industry is considering is restrictive design—limiting the type and placement of features used in designs. Gridding of critical layers significantly reduces the total physical design space available and makes restrictive design possible. This paper will examine the basics of gridding, the requirements for restrictive gridded design, and the automated methods for accurate checking of Restrictive Design Rules (RDRs). Resolving the debug challenges associated with the implementation of checking restrictive design and grid rules will also be discussed.