White Papers

When ST-Ericsson began development of the next-generation U8500 chip, they knew they would face design and implementation challenges. Not only did the U8500 have an aggressive schedule but it also had aggressive design parameters that it needed to achieve. The U8500 had to balance performance, power consumption, and cost, while delivering the complex and sophisticated technology required to support the intensive consumer demands of today’s communications market. The push-button functionality of Calibre SmartFill not only helped ST-Ericsson hit their time-to-market window, but also provided a correct-by-construction approach to control the design and manufacturing variability associated with fill.

This paper discusses the need to analyze and optimize redundancy schemes for embedded memories in SOC designs with the goal of maximizing yield while minimizing impact on chip area and test. Failure mechanisms, repair techniques, and analysis capabilities are described.

Whether you are fabless, fab-lite, or an IDM, the goal of reducing a design's sensitivity to manufacturing issues should ideally be handled by the design teams. The farther downstream a design goes, the less likely a manufacturing problem can be addressed without costly redesign. By addressing DFM problems early, when the design is still in progress, manufacturing ramp-up issues can be avoided.

Mentor Graphics has developed a chip-scale copper electroplating and chemical-mechanical polishing simulator called CMP Optimize. CMP Optimize is part of the Calibre® WORKBench™ platform, and is intended for use with various Design for Manufacturing applications, such as SmartFill optimizations, accurate parasitic extractions, and depth-of-focus variability compensations. CMP Optimize is tightly integrated with Mentor Graphics’ Calibre product line, which provides planarity hotspot detection, as well as thickness analysis and optimization. CMP Optimize is currently the only solution in the industry that gives designers the ability to build models for copper metallization processes. Much like models for lithography, the customer’s process or foundry team builds and owns the copper models. This white paper introduces the CMP Optimize tool from a model-building perspective. It discusses the necessary inputs, model-building methodology from a calibration and optimization standpoint, output data analysis, and model validation capabilities.

This paper documents the results of a critical area and critical feature analysis study of four LSI production 90 nm designs. The recommended rule adherence and statistical sensitivity to random particle defects were evaluated and used to prioritize the yield issues of IP, memories and routing within the various products. Automated correction of recommended rule violations was run in the logic routing to quantify the amount of optimization possible without re-routing the chips. Comparisons were done between the chips to identify commonalities and differences in different design implementations

Fill solutions become more challenging at each smaller node because manufacturing processes and physical interactions become more sensitive to small metal density variations. In addition, the performance of the chip becomes more sensitive to parasitic capacitance (which is increased by adding metal fill) and variations in interconnect resistance (due to CMP impact on metal thickness). Meeting all of these constraints requires better analysis to predict the manufacturing and electrical impacts of fill, and more sophisticated algorithms that optimize the use of metal fill features to solve the three fundamental fill issues. This paper defines the requirements and goals of any fill solution, examines the technology behind Mentor’s four fill solutions, and explains how each can be used to satisfy fill requirements, depending on the needs of the design.

 This paper discusses the features implemented in a Design for Manufacturability (DFM) checker for Critical Feature Analysis of Very Deep Sub-Micron (VDSM) layout designs. This checker leverages Calibre® Yield Analyzer (YA) and Yield Enhancer (YE) functionality, as well as Calibre TCL Verification Format. A central feature of the deck is the identification of opportunities where a layout situation can be improved in a simple, straightforward manner without increasing area inside the top cell boundary. The purpose of such optimization is to increase design robustness to systematic and random yield loss mechanisms and reliability issues without increasing silicon area and cost. An overview of the improvability algorithms implemented using YE features is described, with focus on specific examples of macro code and improvability results on real-life layout cases. Also presented is the use of YA functionality to quantify the gain possible from the application of identified improvements in terms of DFM score. The benefit of this feedback is that it helps designers in prioritizing and selecting the layout improvements to make. Application of the proposed layout optimization flow is finally demonstrated on a 90nm SRAM memory cut design for automotive applications.