Technical Papers

As part of the intellectual property (IP) design process, the IP vendor and the foundry negotiate the “waiver” of certain design rule checking (DRC) errors for the process to which the rule deck is targeted. However, when the IP is integrated into a full-chip design, these errors reappear in the full chip DRC results. With no effective way to identify these errors, chip designers must waste time debugging waived and false errors, and repeating the waiver communication process with the foundry. This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results. This new method enables chip designers to eliminate debug time previously spent on these errors, as well as time spent renegotiating waivers with the foundry. Automated waiver management not only helps designers achieve accurate DRC results in a timely and efficient manner, but also reduces time to market by eliminating unnecessary cycles from the verification flow.

Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, and thus impacts both performance and yield of advanced node chips. To ensure the manufacturability and performance of chips at 22 nm, one approach the industry is considering is restrictive design—limiting the type and placement of features used in designs. Gridding of critical layers significantly reduces the total physical design space available and makes restrictive design possible. This paper will examine the basics of gridding, the requirements for restrictive gridded design, and the automated methods for accurate checking of Restrictive Design Rules (RDRs). Resolving the debug challenges associated with the implementation of checking restrictive design and grid rules will also be discussed.

 This paper provides an overview of Calibre Off-The-Shelf Software (OTSS) validation required by the Food and Drug Administration (FDA) for implantable medical devices. It is based on a Mentor Graphics (MGC) generated Calibre Quality Assurance (QA) document combined with internal Calibre® DRC/LVS in-house testing performed at Boston Scientific (BSC). The following Calibre QA issues will be emphasized first: product lifecycle models, release risk management and monitoring, defect classification, tracking and reporting, functional validation and regression testing, quality metrics. Following the Calibre QA introduction, it will cover these specific topics: project setup, performing Calibre DRC, LVS and XOR tests, regression suite and final results verification scripting, and correlation of vendor assessment of quality versus internal testing outcomes to complete OTSS Calibre validation.

 Complex physical designs (layouts) in 65 nm and below process nodes often use ten (10) or more layers of metallization. So, the length of supply (power/ground) nets as well as that of clock and signal nets is typically long, and the nets involve multiple layers of Vias. These Vias tend to dominate the impedance due to these nets. It is, therefore, often the case that insufficient Via placements on the junctions between Metal(N) and Metal(N+1) turns out to be the root cause of the IR drop failures, and net delays giving rise to setup and hold time violations. The other detrimental effect of Via-deficient junctions is increased heat dissipation and current crowding leading to electro-migration. Wide metals warping resulting in unreliable Via connections require redundant Via placements. Some Via-deficient junctions may barely meet redundant Via requirements, but additional Vias often make the junctions more robust. This paper discusses a simple Perl-Calibre® approach to check for and add Vias to M(N)-M(N+1) junctions that have insufficient Vias or no Vias, but could hold more Vias without violating the topological design rules checks (DRCs). The Vias are checked for and added to junctions on user-specified nets. Although, typically supply nets (VDD,VSS) are handled by the code, there are actually no restrictions on the net names as long as they are top-level net names that can be traced downwards along metal and via lines, or even other connectivity layers.

 Cypress has recently modified the parasitic resistance extraction of Vias and Gates. Rather than use a hard number for PEX VIA REDUCTION COUNT for Via grouping, we have found that using FLEXIBLE PEX VIA REDUCTION RESISTANCE for all layers and allowing user specified application of the "STANDARD COUNT" modifier provides nodal reduction and the ability to increase accuracy if needed. For transistor devices, Cypress extracts parasitic resistance to the center of the seed layer, one half the width of gate. Gates only contacted on one side omit one half of the resistance. Experiments have shown that a more accurate estimation is one third. To achieve that accuracy, our flow now uses RESISTANCE DEVICE_SEED to lower poly resistance. Capacitive accuracy is maintained by treating the gate device as poly a equivalent through the use of CAPACITANCE ALIAS. This paper presents details on the evolution of our parasitic resistance flow.

Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of 2.8% to +3.6% and Idsat change of 10% to +14% are removed from uncertain margin in 45 nm corner libraries.