White Papers
Layout Pattern Dependence-Aware Highly Accurate Simulation Flow with Calibre nmLVS
In today’s nanometer processes, the “layout pattern dependence” that causes variations in the electrical characteristics due to the shape around MOSFETs is becoming more significant. In response to this, NEC Electronics has introduced a highly accurate design environment that takes layout pattern dependence into consideration. For types of dependence not in the SPICE model, development was carried out to introduce a unique model. For neighboring active-area distance dependence (STI stress), the MIRAI-Selete development model was introduced, and for other types of dependence, independent development was carried out at NEC Electronics. This paper describes the development and calibration of these models that was applied to simulation during design using LVS rules that incorporate shape calculations derived by the ADP extraction feature of the Calibre® nmLVS tool.
More White Papers
Analyzing the Device Parasitics Sensitivity and Accuracy of Calibre xACT 3D Field Solver Extraction
As process technologies advance, a parasitic extraction tool requires more sophisticated extraction capability to obtain the effective sensitivity analysis users need, while still meeting schedules and accuracy specifications. Mentor’s new parasitic extraction tool, Calibre® xACT 3D, enabled the Semiconductor Technology Academic Research Center (STARC) to easily and accurately extract the capacitance adjacent to a device on an individual component basis, and create a new reference based on the extraction. With its unique technology and high-quality performance, Calibre xACT 3D can be an integral part of the sophisticated extraction flow needed for today’s complex designs and advanced process technologies.
Describing PERC-based Intent Driven Design
In this paper, we present a fully automated CAD solution that captures the designer’s intent from the schematic netlist, and links these annotations to the proper devices or nets on the physical layout level.
Advanced Memory Cell Characterization with Calibre xACT 3D
Memory designers need to increase bit density to meet exacting specifications for fast data transfer and low power consumption. Higher density increases the interactions between interconnect and devices, yet they have to design with real design margins. Accurate characterization is required at every step of memory design. Memory designers need a tool that can help them analyze parasitic issues accurately and quickly at every stage of the physical design cycle, as well as design cutting-edge memories from basic building blocks to the full chip. Using Calibre xACT 3D at all stages of memory design, from bit cell design to full chip sign-off, ensures a robust design that will work to specification when it is manufactured.
Calibre RealTime: Placing Signoff Verification into the Custom Designer's Hands
Learn how you can reduce custom/AMS design cycle time while improving design quality with on-demand, in-design, signoff-quality verification from Calibre RealTime!
Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs
This paper introduces the first comprehensive and accurate compact resistance-inductance-capacitance-conductance (RLCG) model for through-silicon vias (TSVs) in 3-D ICs valid from low- to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon, the skin effect in TSV metal, and the eddy currents in the silicon substrate. The model is verified against electrostatic measurements as well as a commercial full-wave electromagnetic simulation tool and subsequently employed for various performance (delay) analyses. The compact model is also applicable to TSVs made of carbon nanotube (CNT) bundles, once a slight modification (making the effective conductivity complex) is made. Various geometries (as per the International Technology Roadmap for Semiconductors) and prospective materials (Cu, W, and single-walled/multiwalled CNTs) are evaluated, and a comparative performance analysis is presented. It is shown that CNT-bundle-based TSVs can offer smaller or comparable high-frequency resistance than those of other materials due to the reduced skin effect in CNT bundle structures. On the other hand, the performance (delay) analysis indicates that the performance differences among different TSV materials are rather small. However, it is shown that CNTs provide an improved heat dissipation path due to their much higher thermal conductivity. In addition, the improved mechanical robustness and thermal stability of CNTs also favor their selection as TSV materials in emerging 3-D ICs.
Advanced Manufacturing Closure with Calibre® InRoute and Olympus-SoC
Achieving manufacturing signoff is getting more difficult at each node as we encounter significant manufacturing limitations and variability. This paper describes the physical signoff challenges seen in advanced node designs. It then demonstrates how the Calibre InRoute platform provides faster and more reliable DRC/DFM signoff by using the Calibre verification and DFM platform to drive routing and optimization within the Olympus-SoC place and route environment.
Calibre Pattern Matching: Picture It, Match It...Done!
Calibre Pattern Matching is an extension to SVRF that simplifies complex rule checks required for advanced IC processes. This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.
Calibre xACT 3D — No Compromise Extraction For Advanced Transistor Level Design
Calibre® xACT 3D—a new product designed to provide the reference-level accuracy of a 3D field solver coupled with fast performance and high scalability. Calibre xACT 3D leverages its integration into the established best-in-class production design sign-off flow with Calibre LVS and its device and interconnect modeling infrastructure for maximum usability. This paper details how the Calibre xACT 3D extraction solution addresses the extraction challenges for design signoff at advanced nodes.
Automated DRC Violation Waiver Management for IP Block Integration
As part of the intellectual property (IP) design process, the IP vendor and the foundry negotiate the “waiver” of certain design rule checking (DRC) errors for the process to which the rule deck is targeted. However, when the IP is integrated into a full-chip design, these errors reappear in the full chip DRC results. With no effective way to identify these errors, chip designers must waste time debugging waived and false errors, and repeating the waiver communication process with the foundry. This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results. This new method enables chip designers to eliminate debug time previously spent on these errors, as well as time spent renegotiating waivers with the foundry. Automated waiver management not only helps designers achieve accurate DRC results in a timely and efficient manner, but also reduces time to market by eliminating unnecessary cycles from the verification flow.