Technical Papers
Validation of a New Methodology using VHDL-AMS on a Hard-disk Drive Design
The paper describes the validation of a new methodology using VHDL-AMS on a STMicroelectronics hard-disk drive read/write channel design called "Giotto". The new mixed-signal simulation environment ADVance MS supporting multi-language from Mentor Graphics was used. The objective was to compare the new development of a known circuit designed by current tools. The results showed clearly the great benefice of VHDL-AMS over the former proprietary language HDL-A, and ADVance MS over Eldo-Verilog. The speed performance gain was over 90%. Also developing models with VHDL-AMS was much easier and more efficient. This new methodology is now ready to be adopted by ST for their new generation hard-disk designs.
Phase-Locked Loop Simulation with Modulated Stead-State Analysis
A Fully Automated Approach for Analog Circuit Reuse
Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It is not based on any optimization techniques, but rather relies on a new algorithm based on knowledge extraction, which makes it a very fast technique. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then produces a re-sized design in the target technology with the same performance as the original design. The migration of a low voltage Delta Sigma modulator is presented in this paper to validate the migration engine.
Post-Layout Analysis with Eldo and Eldo RF
Bluetooth Transceiver Design: A Top-Down Flow for Complex RF Mixed-Signal ICs
Modeling and Simulating a ZigBee Wireless Transmitter Path using ADMS RF
Efficient Simulation Techniques for Modulated Delta-Sigma Fractional-N Synthesizers
In this technical paper, we show an efficient simulation methodology for the analysis of spurs in a fractional-N delta-sigma PLL. Delta-sigma PLLs can be used for frequency synthesis or even direct modulation, typically for GMSK or GFSK. The simulators used are Eldo, Eldo RF and ADMS RF.
A delta-sigma PLL is an attractive solution for agile frequency synthesis or even direct modulation. This architecture indeed can meet requirements such as low-power consumption and simple topology, and is suitable for high-level integration.
The goal is to analyze the possible reasons for the presence of said fractional spurs in the output spectrum of a fractional-N delta-sigma PLL for wireless applications, and to show how this can be efficiently simulated.
Bluetooth Transceiver Design with VHDL-AMS
Inductor Device Generators for Automation of RF IC Design
Today's mixed-signal RF IC designs present many challenges and require an integrated, easy-to-use design and verification flow. One of the primary challenges is post-layout verification, where many physical effects impact the quality and performance of the complete design. In situations where rapid pre- to post-layout turnaround is key to meeting project deadlines, new scenarios must be investigated to increase productivity, and trade-offs must be made during the design and verification process.
In this article, we will introduce new inductor device generators, which offer dramatic efficiency increases in the development and automation of RF IC design, layout creation and verification. The flexibility and ease-of-use of these device generators, which fit into the Mentor Graphics AMS SoC Design Flow, make them very attractive to any RF IC Designer.
Design Capture for Analog-Mixed-Signal SoCs-It's Not Just About Entering Schematics Anymore!
As today's mixed-signal SoC designs continue to increase in complexity, functional verification methods are rapidly evolving. Now more than ever, new, more efficient methods of verification must be explored and adopted in order to keep up with the growing demands of SoC design.
Historically, entire designs were represented by a single set of transistor-level schematics, with each individual component, as well as the entire design itself, being functionally verified using a digital gate-level and or analog transistor-level simulator. In today's SoC designs, the necessity to incorporate reusable IP from multiple sources requires that both VHDL and Verilog modeling languages must be supported in the simulation environment. To efficiently address this requirement, functional verification must now take place in a single kernel simulation environment, with the ability to trace simulation results back to appropriate source code line in Verilog or VHDL. Additionally, there must be a means by which to co-simulate sensitive analog functions using traditional SPICE and advanced analog RF algorithms. There are also the emerging standard analog and mixed-signal functional modeling languages VHDL-AMS (IEEE 1076.1), Verilog- A, and Verilog-AMS. These languages are becoming popular as alternatives to the traditional means of drawing transistor-level schematics to enter analog and mixed-signal types of components.