Technical Papers
Full Chip Model Based Correction of Flare-Induced Linewidth Variation
Litho Friendly Design Kit: A Tool of DFM Strategy
For deep sub micron technologies, ensuring good yield is becoming challenging. STMicroelectronics has implemented, as a part of its DFM strategy, a methodology based upon LFD. It provides, at design level, a CAD solution to assist end users in targeting good printability over the whole process window and across a wide number of environments. An LFD kit creator has been implemented to fully automate the LFD kit generation based on OPC/RET recipes and models. The kit allows the detection of hot spots, the simulation of gates and interconnects contours. For large blocks or full chips, a Fast mode is also implemented. In addition, a way to calibrate such an LFD kit has been put in place which consists in guaranteeing the alignment with respect to silicon data. To compare the different approaches of DFM strategy, an analysis is driven between model-based (LFD) and a rule-based approach (ST's DFM Toolbox Solution based on CFA). The accuracy, run time and sensitivity are analyzed in detail.
Pixel-based SRAF Implementation for 32nm Lithography Process
A Pixel-based sub-resolution assist feature (SRAF) insertion technique has been considered as one of the promising solutions by maximizing the common process window. However, process window improvement of the pixel-based SRAF technique is limited by the simplification of SRAFs for mask manufacturability. Mask simplification and mask rule check (MRC) constraints parameters for pixel-based SRAF technique are the critical factors for mask production without a big loss of its benefit. In this study, correlation of MRC control was analyzed in terms of the robustness to process variation for a contact layer of 32nm device node. An optimum condition of MRC constraints was selected by balancing the process window and mask manufacturability. In addition, a novel and practical methodology for 32nm device node development was proposed to keep the mask complexity low and to take full advantage of process window improvement using pixel-base SRAF insertion.
Double-patterning Decomposition, Design Compliance, and Verification Algorithms at 32nm hp
Double patterning (DP) technology is one of the main candidates for RET of critical layers at 32nm hp. DP technology is a strong RET technique that must be considered throughout the IC design and post tapeout flows. We present a complete DP technology strategy including a DRC/DFM component, physical synthesis support and mask synthesis. In particular, the methodology contains: - A DRC-like layout DP compliance and design verification functions; - A parameterization scheme that codifies manufacturing knowledge and capability; - Judicious use of physical effect simulation to improve double-patterning quality; - An efficient, high capacity mask synthesis function for post-tapeout processing; - A verification function to determine the correctness and qualify of a DP solution; Double patterning technology requires decomposition of the design to relax the pitch and effectively allows processing with k1 factors smaller than the theoretical Rayleigh limit of 0.25. The traditional DP processes Litho-Etch-Litho- Etch (LELE) [1] requires an additional develop and etch step, which eliminates the resolution degradation which occurs in multiple exposure processed in the same resist layer. The theoretical k1 for a double-patterning technology applied to a 32nm half-pitch design using a 1.35NA 193nm imaging system is 0.44, whereas the k1 for a single-patterning of this same design would be 0.22 [2], which is sub-resolution. This paper demonstrates the methods developed at Mentor Graphics for double patterning design compliance and decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. It also demonstrates verification solution implementation in the chip design flow and post-tapeout flow.
Non-Uniform Yield Optimization for Integrated Circuit Layout Considering Global Interactions
In a previous work we have shown a yield optimization metric and a technique that considers the effects of several types of yield enhancement methods for a given layout. Those findings suggested that it is important to consider two types of yield tradeoffs, local tradeoffs where addressing one yield loss mechanism degrades others in the immediate vicinity of the correction (local optimization window), and global tradeoffs where the net effect of the correction can be fully accounted only when considering neighboring optimization windows. Such conclusion was derived from the fact that the locally optimized layouts did not completely realize the theoretically optimal yield, which was obtained from the assumption that global tradeoffs could be fully resolved. This work focuses in the contribution that such global tradeoffs have on the final yield score when accounted properly during the optimization. While the previous work focused only in selecting the corrections that locally improved the yield score1, this work evaluates the global interactions before and after a change, and the correction is only accepted if it improves the global score. While the global optimization requires a more expensive computational process, the intention of this work is to determine how close the optimal layout can be from its theoretical limit. Since the optimization is performed and evaluated under four different types of processes in which the failure mechanisms vary in relative importance, it is possible to derive conclusions as to the need of considering global effects when trading off runtime requirements with quality of the correction.
Adaptive Automatic Fragmentation
As more aggressive Resolution Enhancement Techniques (RET) are applied, the problem of correctly fragmenting edges of an OPC mask is becoming more complex. OPC recipes contain more lines devoted to control of fragmentation than anything else. This paper introduces a new Automatic Adaptive Fragmentation method that decreases the complexity of OPC recipes while providing the same or better quality of results. The adaptive fragmentation is guided by just a few simple rules that provide flexible fragmentation while adhering to mask manufacturing rule constraints.
Simultaneous Model-based Main Feature and SRAF Optimization for 2D SRAF Implementation to 32 nm Critical Layers
Sub-resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for the optimum placement of 2D SRAF structures using state of the art Calibre RET flow. In this approach, the optimal SRAF shapes are achieved simultaneously during the OPC step. The SRAF and main features are optimized to account for their edge placement and process window metrics (aerial image slope/contrast, out of focus/dose EPE, etc…). The resulting mask shapes deliver some of the properties that can be obtained using the Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost no impact on the runtime. The implemented model-based optimization flow remains compatible with the current OPC production flows.
Automatic Assist Feature Placement Optimization Based on Process-Variability Reduction
To maximize the process window and CD control of main features, sizing and placement rules for sub-resolution assist features (SRAF) need to be optimized, subject to the constraint that the SRAFs not print through the process window. With continuously shrinking target dimensions, generation of traditional rule-based SRAFs is becoming an expensive process in terms of time, cost and complexity. This has created an interest in other rule optimization methodologies, such as image contrast and other edge- and image-based objective functions. In this paper, we propose using an automated model-based flow to obtain the optimal SRAF insertion rules for a design and reduce the time and effort required to define the best rules. In this automated flow, SRAF placement is optimized by iteratively generating the space-width rules and assessing their performance against process variability metrics. Multiple metrics are used in the flow. Process variability (PV) band thickness is a good indicator of the process window enhancement. Depth of focus (DOF), the total range of focus that can be tolerated, is also a highly descriptive metric for the effectiveness of the sizing and placement rules generated. Finally, scatter bar (SB) printing margin calculations assess the allowed exposure range that prevents scatter bars from printing on the wafer.
Subsystem Exchange in a Concurrent Design Process Environment
This paper provides insight into the novel solutions used to build SoCs targeting increased productivity in a complex environment. Design of such SoCs relies on multi-team, multi-site cooperation and data exchange. The data exchange, made possible though descriptions based on The SPIRIT Consortium’s IP-XACT™ specification and the automation for its processing, forms the basis of the approach. Initially, the specification focused at IP reuse; this has now been extended to SoC subsystem exchange. This paper also describes state-of-the-art subsystem design automation and improvement opportunities, based on a close collaboration between NXP Semiconductors and Mentor Graphics. We do not cover all the aspects of reuse but mainly stress the concurrent engineering process.
Implementation of Adaptive Site Optimization in Model-Based OPC for Minimizing Ripples
The OPC treatment of aerial mage ripples (local variations in aerial contour relative to constant target edges) is one of the growing issues with very low-k1 lithography employing hard off-axis illumination. The maxima and minima points in the aerial image, if not optimally treated within the existing model based OPC methodologies, could induce severe necking or bridging in the printed layout.
The current fragmentation schemes and the subsequent site simulations are rule-based, and hence not optimized according to the aerial image profile at key points. The authors are primarily exploring more automated software methods to detect the location of the ripple peaks as well as implementing a simplified implementation strategy that is less costly. We define this to be an adaptive site placement methodology based on aerial image ripples.
Recently, the phenomenon of aerial image ripples was considered within the analysis of the lithography process for cutting-edge technologies such as chromeless phase shifting masks and strong off-axis illumination approaches. Effort is spent during the process development of conventional model-based OPC with the mere goal of locating these troublesome points. This process leads to longer development cycles and so far only partial success was reported in suppressing them (the causality of ripple occurrence has not yet fully been explored). We present here our success in the implementation of a more flexible model-based OPC solution that will dynamically locate these ripples based on the local aerial image profile nearby the features edges. This model-based dynamic tracking of ripples will cut down some time in the OPC code development phase and avoid specifying some rule-based recipes.
Our implementation will include classification of the ripples bumps within one edge and the allocation of different weights in the OPC solution. This results in a new strategy of adapting site locations and OPC shifts of edge fragments to avoid any aggressive correction that may lead to increasing the ripples or propagating them to a new location. More advanced adaptation will be the ripples-aware fragmentation as a second control knob, beside the automated site placement.