Confronting Chip Assembly Challenges
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Contributor: Sudhakar Jilla, Director of Marketing, Place and Route Division, Mentor Graphics Corp. Format: PDF Document At nanometer technologies, IC physical design teams are designing multi-million gate products with very complex functionality including different processor cores, memory blocks, and analog circuitry on a single chip. In addition to addressing the sheer size and complexity, designers also need to deal with variations in design modes, environmental conditions, manufacturing steps, and device and interconnect behavior. In recent years, hierarchical approaches have gained traction for the implementation of multi-million gate SOCs. However, at these design sizes, flows using the current-generation of physical implementation severely strained to meet the chip specifications with aggressive schedules. |