Technical Papers
Reducing Physical Verification Cycle Time
As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.
Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.
Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.
Implementation-Quality Prototyping With Olympus-SoCTM: Accelerating Design Closure for Advanced ICs
The growing complexity of today’s ICs and tight market schedules are driving a demand for more powerful solutions for design prototyping. Prototyping helps designers determine the feasibility of implementing a particular design given the various requirements. By using Olympus-SoC for rapid prototyping early in the design cycle, designers can catch issues with macro placement, missing constraints, RTL problems, and many other design problems. In this paper, we show how design prototyping with the Mentor Graphics Olympus-SoC physical implementation system improves predictability and facilitates design closure.
Confronting Chip Assembly Challenges: Avoid Late-Stage Bottlenecks in Physical Design
The increasing size and complexity of today’s multi-million gate SoCs necessitates hierarchical chip design methodologies, which partition the chip into smaller pieces. A hierarchical methodology is necessary for large SoCs because it extends the capacity of design-automation tools, improves tool runtimes, and limits last minute design changes. However, even hierarchical flows using the current-generation of physical implementation tools are facing problems closing the chip requirement within aggressive schedules. In this paper, we review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.
Calibre OTSS Validation for Medical Applications
This paper provides an overview of Calibre Off-The-Shelf Software (OTSS) validation required by the Food and Drug Administration (FDA) for implantable medical devices. It is based on a Mentor Graphics (MGC) generated Calibre Quality Assurance (QA) document combined with internal Calibre® DRC/LVS in-house testing performed at Boston Scientific (BSC). The following Calibre QA issues will be emphasized first: product lifecycle models, release risk management and monitoring, defect classification, tracking and reporting, functional validation and regression testing, quality metrics. Following the Calibre QA introduction, it will cover these specific topics: project setup, performing Calibre DRC, LVS and XOR tests, regression suite and final results verification scripting, and correlation of vendor assessment of quality versus internal testing outcomes to complete OTSS Calibre validation.
Reducing IC Cycle Time with Calibre
Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physical verification should take longer and why we should be given more time than we had for our previous project. As nice as that would be, this is not the case. Increasing competitive environments and the always present compulsion to get products out to market in a timely manner have not permitted such luxuries. Fortunately, despite conspiring forces to elongate this already difficult task, there is a light at the end of the tunnel (no, not a train coming the other direction), the Calibre suite of verification tools, specifically Calibre nmDRC, Calibre nmLVS and Calibre Incremental DRC.
Implementation-Quality Prototyping With Olympus-SoCTM: Accelerating Design Closure for Advanced ICs
Not Your Daddy's DRC: Calibre nm
Further Reducing the High Cost of Processing Power
processing of design data an essential part of design-to-silicon flows.
To achieve profitability, design houses and fabs alike must be able to
process huge and complicated volumes of design data swiftly. Turn around
time (TAT) must be held to a minimum to ensure that designs are readied
for manufacturing as quickly as possible in order to keep costs low and
take advantage of volatile windows of opportunity in the marketplace.
With Calibre(r) MT or MTflex, TAT is reduced and throughput is
increased. For large IDMs or foundries that must process several jobs,
hardware configurations can be better utilized to optimize the total
number of jobs that can run through in any given day.
Litho-Friendly Design: Capturing Process Variability for the Design Flow
However, in order for a DFM recommendation to be of value to designers, it must include details about how a particular design will manufacture given the specific process. This requires a tool that can communicate an awareness of the process window at all stages of the design flow. This capability is the key benefit of an advanced DFM technology known as litho-friendly design (LFD), the goal of which is to capture process variability to improve layout robustness.
A Fully Automated Approach for Analog Circuit Reuse
Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It is not based on any optimization techniques, but rather relies on a new algorithm based on knowledge extraction, which makes it a very fast technique. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then produces a re-sized design in the target technology with the same performance as the original design. The migration of a low voltage Delta Sigma modulator is presented in this paper to validate the migration engine.