Technical Papers

Sign-off for IC tape-out has undergone dramatic changes over the past several years. The size and complexity of nanometer IC design and the volume of geometric content for related layouts all skyrocketed. Additionally, extensive changes occurred in the processing requirements for nanometer design processes. Physical impacts that we once could ignore now have measurable electrical effects.

As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.

Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.

Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.

In this white paper we discuss how Pinnacle's prototyping capabilities add significant value to current design flows. We first discuss how Pinnacle Prototyping helps engineers in the early design phase to refine and finalize the floorplan and complex design constraints. Next, we show how Pinnacle can save months by accounting for late stage effects: timing problems seen at various operating modes or corners, on-chip variation induced setup and hold violations, power issues seen later in design flow due to multi-corner and multi-mode fixing, and clock tree synthesis related congestion. Pinnacle gives designers the ability to identify these implementation issues early in the design cycle. By using Pinnacle Prototyping designers can significantly reduce time to best results.

The characteristics of today's complex IC designs are making accelerated
processing of design data an essential part of design-to-silicon flows.
To achieve profitability, design houses and fabs alike must be able to
process huge and complicated volumes of design data swiftly. Turn around
time (TAT) must be held to a minimum to ensure that designs are readied
for manufacturing as quickly as possible in order to keep costs low and
take advantage of volatile windows of opportunity in the marketplace.
With Calibre(r) MT or MTflex, TAT is reduced and throughput is
increased. For large IDMs or foundries that must process several jobs,
hardware configurations can be better utilized to optimize the total
number of jobs that can run through in any given day.

Traditionally, after the hand-off of a design, it has been the foundry's responsibility to ensure printability. But with process technologies of 90nm and below, the entire design flow is susceptible to yield inhibitors. That's why designers, foundries and EDA toolmakers are turning to design-for-manufacturing (DFM) methodologies that promise improved flows and solutions that manage and analyze nanometer effects.
However, in order for a DFM recommendation to be of value to designers, it must include details about how a particular design will manufacture given the specific process. This requires a tool that can communicate an awareness of the process window at all stages of the design flow. This capability is the key benefit of an advanced DFM technology known as litho-friendly design (LFD), the goal of which is to capture process variability to improve layout robustness.