White Papers

Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light diraction eects limit the resolution of pattern with ever smaller dimension in ArF lithography using a fixed exposure wave length of 193nm and prevent printing wafer patterns identical to the shapes drawn on the exposure mask. Resolution enhancement techniques such as Optical Proximity Correction (OPC) enable new technologies to be realized in wafer manufacturing. Sub-resolution assist features (SRAF), or scatter bars (SB), provide critical process window enhancements in the lithography process. Traditionally, SRAF generation is based on geometric rules, which are extracted from a large amount of simulation and empirical wafer data from printing test masks.

With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the current process, schematic designers go through extensive simulations to cover all the possible variations of their design parameters and hence of the design functionality. At the same time, layout designers perform time-consuming process-aware simulations (such as lithography simulations) on the full chip layout, which impacts the design turn-around time. In this paper, we present a fast physical layout and electrical-aware Design-For-Manufacturability (DFM) solution that detects hotspot areas in the full chip design without requiring extensive electrical and process simulations. Novel algorithms are proposed to implement the engines that are used to develop this solution. Our proposed flow is examined on a 45 nm industrial Finite Impulse Response (FIR) full chip. The proposed methodology is able to define a list of electrical hotspot devices located on the FIR critical path that experience up to 17% variation in their DC current values due to the effect of process and design context. The total runtime needed to identify and detect these electrical hotspots on the FIR full chip takes nearly 3 minutes, compared to hours when using conventional electrical and process simulations.

This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. We discuss and present the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. We also share the detailed statistics regarding run time, machine resource, data size, polygon counts etc. We also present good techniques used by us for efficient flow management involved in large complex 28nm chips. These results were verified at GlobalFoundries.

In this work, we introduce the use of pattern matching as a potential solution for many verification flows problems. Pattern matching offers a great TAT advantage since it is a DRC based process, thus it is much faster than time consuming LITHO operations. Also, its capability to match geometries directly and operability on many layers simultaneously eliminates complex SVRF coding from our flows. Firstly, we will use the pattern matching in order not to run OPC verification on basic designs identified by the OPC engineer to be error free, which is a very useful technique especially in Memory designs and improves the run time. Then, it will be used to detect waivers, which is hard to code, while running verification flows and eliminate it from the output, and consequently the reviewer will not be distracted by it and concentrate on real errors. And finally, it will be used to detect hot spots in a separate very quick run before standard LITHO verification run which gives the designer/OPC engineer the opportunity to fix design/OPC issues without waiting for lengthy verification flows, and that in turns further improves TAT.

Microsemi qualified a structured approach to mixed-signal SoC verification using Questa ADMS, systematic pre-planning, and the OVM. The special requirements of interfacing to the mixed-signal DUT are encompassed by a library of driver and monitor extension elements that we call O-SRC and O-PRB. We report on the verification plan, the development effort, the results achieved, and our conclusions regarding the viability of these techniques for future product development at Microsemi.

A methodology of advanced process window simulations with awareness of chip topology is presented. This method identifies the expected focal range encountered due to different topology in different areas within a design. As a result, respective defocus models are used to drive the LFD simulations and detect CD (Critical Dimension) variations in printing features. By building process models to be implemented, we can attempt to pinpoint process hotspots based on where they would appear on a real wafer. Identified hotspots are then compared to real wafer results, and a practical use of these results is fed to OPC. Finally all hotspots are enhanced by OPC with applied focus shifting instead of design revision.