White Papers
Restrictive Design Rules and Their Impact on 22 nm Design and Physical Verification
Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, and thus impacts both performance and yield of advanced node chips. To ensure the manufacturability and performance of chips at 22 nm, one approach the industry is considering is restrictive design—limiting the type and placement of features used in designs. Gridding of critical layers significantly reduces the total physical design space available and makes restrictive design possible. This paper will examine the basics of gridding, the requirements for restrictive gridded design, and the automated methods for accurate checking of Restrictive Design Rules (RDRs). Resolving the debug challenges associated with the implementation of checking restrictive design and grid rules will also be discussed.
More White Papers
Calibre RealTime: Placing Signoff Verification into the Custom Designer's Hands
Learn how you can reduce custom/AMS design cycle time while improving design quality with on-demand, in-design, signoff-quality verification from Calibre RealTime!
Advanced Manufacturing Closure with Calibre® InRoute and Olympus-SoC
Achieving manufacturing signoff is getting more difficult at each node as we encounter significant manufacturing limitations and variability. This paper describes the physical signoff challenges seen in advanced node designs. It then demonstrates how the Calibre InRoute platform provides faster and more reliable DRC/DFM signoff by using the Calibre verification and DFM platform to drive routing and optimization within the Olympus-SoC place and route environment.
Calibre Pattern Matching: Picture It, Match It...Done!
Calibre Pattern Matching is an extension to SVRF that simplifies complex rule checks required for advanced IC processes. This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.
Automated DRC Violation Waiver Management for IP Block Integration
As part of the intellectual property (IP) design process, the IP vendor and the foundry negotiate the “waiver” of certain design rule checking (DRC) errors for the process to which the rule deck is targeted. However, when the IP is integrated into a full-chip design, these errors reappear in the full chip DRC results. With no effective way to identify these errors, chip designers must waste time debugging waived and false errors, and repeating the waiver communication process with the foundry. This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results. This new method enables chip designers to eliminate debug time previously spent on these errors, as well as time spent renegotiating waivers with the foundry. Automated waiver management not only helps designers achieve accurate DRC results in a timely and efficient manner, but also reduces time to market by eliminating unnecessary cycles from the verification flow.
Equation-Based DRC: A Novel Approach to Resolving Complex Nanometer Design Issues
Traditional physical verification uses single-dimensional design rule checks (DRC) to identify sensitive layout features likely to fail during manufacturing. Checks that require coding large tables of measurement thresholds are extremely difficult to implement using traditional DRC approaches. A new technique, known as Equation-Based DRC (eqDRC), extends traditional DRC to define grouped multi-dimensional feature measurements using flexible mathematical expressions, providing a customizable physical modeling tool and enabling the analysis of complex interactions that could not previously be verified. This paper will examine the implementation and demonstrate the benefits of eqDRC through a variety of examples comparing traditional DRC with eqDRC approaches.