White Papers

With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the current process, schematic designers go through extensive simulations to cover all the possible variations of their design parameters and hence of the design functionality. At the same time, layout designers perform time-consuming process-aware simulations (such as lithography simulations) on the full chip layout, which impacts the design turn-around time. In this paper, we present a fast physical layout and electrical-aware Design-For-Manufacturability (DFM) solution that detects hotspot areas in the full chip design without requiring extensive electrical and process simulations. Novel algorithms are proposed to implement the engines that are used to develop this solution. Our proposed flow is examined on a 45 nm industrial Finite Impulse Response (FIR) full chip. The proposed methodology is able to define a list of electrical hotspot devices located on the FIR critical path that experience up to 17% variation in their DC current values due to the effect of process and design context. The total runtime needed to identify and detect these electrical hotspots on the FIR full chip takes nearly 3 minutes, compared to hours when using conventional electrical and process simulations.

This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. We discuss and present the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. We also share the detailed statistics regarding run time, machine resource, data size, polygon counts etc. We also present good techniques used by us for efficient flow management involved in large complex 28nm chips. These results were verified at GlobalFoundries.

A methodology of advanced process window simulations with awareness of chip topology is presented. This method identifies the expected focal range encountered due to different topology in different areas within a design. As a result, respective defocus models are used to drive the LFD simulations and detect CD (Critical Dimension) variations in printing features. By building process models to be implemented, we can attempt to pinpoint process hotspots based on where they would appear on a real wafer. Identified hotspots are then compared to real wafer results, and a practical use of these results is fed to OPC. Finally all hotspots are enhanced by OPC with applied focus shifting instead of design revision.

This paper discusses the need to analyze and optimize redundancy schemes for embedded memories in SOC designs with the goal of maximizing yield while minimizing impact on chip area and test. Failure mechanisms, repair techniques, and analysis capabilities are described.

Whether you are fabless, fab-lite, or an IDM, the goal of reducing a design's sensitivity to manufacturing issues should ideally be handled by the design teams. The farther downstream a design goes, the less likely a manufacturing problem can be addressed without costly redesign. By addressing DFM problems early, when the design is still in progress, manufacturing ramp-up issues can be avoided.

Mentor Graphics has developed a chip-scale copper electroplating and chemical-mechanical polishing simulator called CMP Optimize. CMP Optimize is part of the Calibre® WORKBench™ platform, and is intended for use with various Design for Manufacturing applications, such as SmartFill optimizations, accurate parasitic extractions, and depth-of-focus variability compensations. CMP Optimize is tightly integrated with Mentor Graphics’ Calibre product line, which provides planarity hotspot detection, as well as thickness analysis and optimization. CMP Optimize is currently the only solution in the industry that gives designers the ability to build models for copper metallization processes. Much like models for lithography, the customer’s process or foundry team builds and owns the copper models. This white paper introduces the CMP Optimize tool from a model-building perspective. It discusses the necessary inputs, model-building methodology from a calibration and optimization standpoint, output data analysis, and model validation capabilities.

This paper documents the results of a critical area and critical feature analysis study of four LSI production 90 nm designs. The recommended rule adherence and statistical sensitivity to random particle defects were evaluated and used to prioritize the yield issues of IP, memories and routing within the various products. Automated correction of recommended rule violations was run in the logic routing to quantify the amount of optimization possible without re-routing the chips. Comparisons were done between the chips to identify commonalities and differences in different design implementations