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Circuit Verification with Calibre®

Calibre's circuit verification strategies and tools effectively and efficiently address the reliability and functional yield challenges of today's advanced and complex IC designs.

Overview

Circuit Verification involves several essential steps in the design process that will help identify potential circuit or design errors as well as extract the necessary data for downstream circuit simulation. During this step, layout is analyzed and compared vs. the schematic to ensure design integrity. Second, the design is analyzed for short-term and long-term electrical failures and, if found, those are presented to the designer for fixing. And finally, a detailed silicon model is constructed with intentional device, advanced parameters, and parasitic information into a format that consumed by a downstream simulator so that designers can reliably determine if their design is meeting electrical specifications (timing, power, etc.)

Products

Calibre xRC

Calibre xRC™ offers a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.  View Product Overview

Calibre nmLVS

Calibre nmLVS™, the industry-leading physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging. View Product Overview

Calibre PERC

Calibre® PERC is specifically designed to perform electrostatic discharge (ESD) and multiple power domain checks. Calibre PERC allows you to customize ERC checks at the... View Product Overview

Calibre xACT 3D

Calibre® xACT 3D delivers high performance parasitic RC extraction featuring the reference-level accuracy of a deterministic field solver combined with the production turnaround performance of traditional... View Product Overview

Calibre xL

Full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency. Fully integrated with Calibre nmLVS... View Product Overview

Features and Benefits

  • Accurate modeling of electrical circuit behavior for "as-built" layouts
  • Increased IC reliability through checks for ESD protection
  • Automated checking of complex electrical rules
  • More robust checking of electrical circuits at advanced nodes
  • Accurate modeling of devices and interactions between devices
  • Customer-defined device parameters
  • Detailed modeling of interconnect interactions
  • The underlying hierarchical processing engine ensures robust testing and implementation across all applications, while providing best-in-class runtimes.
  • The only 5-Star support in EDA
  • Common design platform integration enables rapid deployment of all Calibre® nm Platform applications into the user’s design environment.
  • Integrated scripting environment across all applications (SVRF and TVF) allow users to customize their design and verification environment to suit the specific and evolving needs of their design teams.
  • Hyperscaling technology brings superior scalability and lightening fast run times for computationally intense applications, while reducing capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilizing inexpensive distributed rack systems.

“Calibre offers a unique combination of performance, accuracy, and capability allowing us to implement an optimal recipe for our 0.095 micron process. Calibre is already in use with our 0.180 and 0.150 micron technologies, and NEC is aggressively moving forward with advanced semiconductor processes. Calibre is a key enabler in accelerating this schedule.”

Dr. Kazuhiko Takamizawa Senior Manager of System LSI Design Engineering Division

Circuit Verification Resources

“Calibre's extensive rule file coverage, design-style independence and on-time customer support made it the best choice for the complex designs our customers are creating. Selecting Calibre ensures customers a confident design transfer and a smooth manufacturing process.”

Stephen Kuo Design Service Department Manager, Technology Development Unit

 
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