Calibre nmLVS

Calibre® nmLVS, the market-leading layout vs. schematic physical verification tool, is tightly linked with both Calibre nmDRC and Calibre xRC to deliver production-proven device extraction for both physical verification and parasitic extraction. Calibre nmLVS performs a vital function as a member of a complete IC verification tool suite by providing device and connectivity comparisons between the IC layout and the schematic. Calibre's hierarchical processing engine runs Calibre nmLVS, supplying data for modifying the IC design to achieve superior functionality and reliability.

Accurate Circuit Verification

Calibre nmLVS enables accurate circuit verification because it is able to measure actual device geometries on a full-chip for a complete accounting of physical parameters. These precise device parameters supply the information for back-annotation to the source schematic and the comprehensive data for running simulations. In addition to working with Calibre xRC, Calibre nmLVS can also be used with third party parasitic extraction tools.

Automate Advanced, Customer-Specific ERCs

Calibre nmLVS can now be enhanced with Calibre PERC (Programmable Electrical Rule Checker). With Calibre PERC, you can automate advanced, customer-specific ERCs to eliminate lengthy and error-prone manual checking. PERC recognizes grouped devices that are connected as you describe and measures geometrical data associated with the circuit topology.

Features and Benefits

Market Leadership

Calibre nmLVS continues to lead the market. Preferred by engineers and management for its proven performance, capacity, reliability and debug ease-of-use.

Best-in-Class Accuracy

De­vice recognition accuracy is cru­cial for tape-out success. Calibre nmLVS delivers the trusted device recognition accuracy and timely execution required for world-class silicon delivery.

Fast Runtime

Automated proprietary hierarchical and logic injection technologies provide virtually unlimited design scope with fast runtimes. Multi-threaded and distributed CPU processing capabilities ensure future proof scaling on your hardware.

Flexibility

Calibre nmLVS is ideally suited for processing any size job requiring intricate device parameter extraction, whether it’s an analog/RF design or a multi­million gate IC.

Reliability

With thousands of users, Calibre nmLVS sets the standard for reliability and pre­dictability in all operations.

Design Debugging and Ease-of-Use

Calibre nmLVS provides an intuitive and easy-to-use inte­grated design verification debug­ging environment to help you find and fix design issues. Calibre® nmLVS is two to three times faster than traditional layout vs. schematic processes.

A Closer Look

Calibre nmLVS

This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow.

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Calibre nmLVS Integrated Design Debug Environment DemonstrationOn-demand Web Seminar

Datasheet

Toolbox

“Mentor's Calibre nmLVS product with the ADP extraction feature enables us to extract highly-accurate circuit characteristics better reflecting our industry-leading semiconductor processes by taking into account systematic variation of layout context among the transistors themselves, and within the surrounding region...”

Haruji Futami, Senior Manager -Core Development Division, NEC