Calibre® xRC™ is a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. Calibre xRC is able to extract interconnect parasitics hierarchically.
The result is a compact, hierarchical, transistor-level parasitic data, which can be back-annotated and simulated with full-chip circuit simulation tools, such as HSIM. By using hierarchical storage and leveraging the circuit hierarchy and isomorphism during simulation, Calibre xRC and HSIM achieve breakthrough performance for very large circuits, while delivering detailed SPICE-level accuracy.
Features and Benefits
- Delivers unparalleled performance on ASIC, memory, analog, SoC designs, etc. with no trade-off in accuracy
- Single rule file can drive DRC, LVS, and Calibre xRC functionality
- Reads LVS data structures to integrate parasitic information with intentional circuit elements
- Model-based engine calculates intrinsic and coupling capacitances for all nets using the same high degree of accuracy
- Integrates with Calibre DRC™ and LVS, Calibre Interactive™, Calibre View and Calibre RVE™, which offer powerful verification and cross-probing capabilities
- Extraction and simulation results correlate closely with silicon measurements
- Offers AMS SoC designers a single parasitic extraction solution that is independent of design style or flow
Calibre xRC FAQs
Have general questions about parasitic extraction? Or specific questions about Calibre xRC, check out these frequently asked questions to find the answer. FAQ...