A. Parasitic extraction is the process of creating an electrical model representation of the physical interconnections present between devices in an integrated circuit.
A. From a technical viewpoint, the physical interconnect (especially for 0.35um processes and below) does not behave as a virtual or ideal wire. Instead, it acts similarly to a network of capacitances and resistors, which can dominate circuit behavior, particularly with regard to timing. These interconnect parasitics become increasingly prevalent as process geometries shrink below .35u or Deep Sub-Micron (DSM).
A. Calibre xRC is an integral component of our strategy. Complex IC design requires 1) verification that the layout matches the source schematic and 2) extraction of parasitic devices so analysis can accurately predict how the circuitry will behave when manufactured. Therefore, extraction must create an accurate netlist for downstream analysis. It doesn't do much good to do power or timing analysis of a design without the parasitic resistances and capacitances that will show up in the DSM manufacturing process.
A. There will always be multiple tools for simulation and analysis of the design, but there are tremendous benefits in using closely-tied verification and extraction tools. Both must use and operate on process model information from manufacturing, and both perform an extraction process on the design. LVS extracts the intended devices and parasitic extraction extracts the unintended resistances and capacitances that occur. Using a single-tool flow for verification and extraction provides results that are consistent across this flow. Calibre LVS and Calibre xRC use the same data and rule files and Calibre xRC reads Calibre LVS structures directly.
A. If you have different verification and extraction tools, there is a real possibility that there will be inconsistencies between the LVS results and the extraction results. As a designer, you don't know which is more accurate. So you may be forced to over-engineering the design to minimize the potential of having the circuit not meet spec when it is manufactured. Consistency of results across verification and extraction gives you confidence that the design will perform as intended when it is manufactured.
A. One of the major benefits of Calibre xRC is that it works directly with Calibre LVS, the leading LVS tool for DSM design. This gives you the confidence of a single-tool flow as described above. In addition, the Calibre xRC tool has several key features which differentiate it from other products. Among these are: a very accurate extraction engine at the gate and transistor level, design-style independence, the ability to extract selected nets, back annotation of parasitic information to the source, and the ability to work with a wide range of popular input and output formats. Also, extraction can create a massive amount of datA. This can present a problem for downstream analysis programs. In preparing data for analysis, Calibre xRC has a database formatter that will postprocess extraction data depending on the type of simulation or analysis being performed.
A. Extraction is normally performed at the transistor level, where every primitive device in the circuit is considered, or at the gate level, where extraction stops at the pins of gates. Some extraction tools require you to use a different process or procedure depending on the level of extraction. With Calibre xRC, however, the extraction set-up and process is the same regardless of the level of extraction.
A. All of our competitors have holes somewhere in their offerings, whether it be the weakness of the LVS-extraction link, substandard transistor-level performance and accuracy, or weak technical support. Calibre xRC does not have any of those limitations. In fact, they are our strong points. Also, most of the competition concentrates on the process of extraction (where the Calibre xRC engine outperforms its rivals anyway). This is important, but it's not the entire solution. As indicated above, preparation of the data for analysis greatly facilitates the design process. And by working with popular inputs and outputs, Calibre xRC enables the physical analyses that are critical to successful DSM IC production, without locking you into a particular vendor's suite of tools.
A. We are committed to making you successful with Calibre xRC. So we provide first-rate technical support both before the sale, helping you evaluate Calibre xRC in your design environment, and after the sale, helping to resolve any problems that might come up. Our award-winning* support team includes extraction-savvy application and support engineers in our regional offices, in our Calibre xRC product group, and in our technical support center. And if you use Calibre LVS with Calibre xRC, one call to Mentor Graphics will get you support for either tool. This is another benefit of using a single-tool verification-extraction flow.
*Mentor Graphics' customer support team has won the prestigious STAR (Software Technical Assistance Recognition) Award from the Software Support Professional Association for the fifth time in ten years.
A. Parasitic extraction with Calibre xRC is accomplished by the following components.
A. The main feature of the FDB is that net data is entirely "free" of any virtual hierarchical boundaries imposed by the CAD database. The net can be captured from device terminal to device terminal, making no assumptions about dangling segments or drive loads. The FDB contains connectivity and geometrical information about a net, independent of how the net may traverse the design hierarchy. The FDB enables a designer to extract on a per-net basis, depending on the level of detail desired.
A. The PDB contains electrical models of the parasitic effects of the physical interconnect of a design. These models can be formatted to the required level of abstraction for annotation to any front-end design description. This prevents any post-layout analysis being restricted by the historically flat or uni-leveled output of an extraction engine.
A. The whole reason for the innovative Calibre xRC flow is to address the requirement for post-layout analysis of DSM designs. Downstream analyses have always been constrained by the output of the extraction engines, such as a flat SPICE netlist. In other words, simulation was driven by the limitations of the LPE tool. Calibre xRC enables simulation of layout, including the parasitic effects of the passive interconnect, at any or mixed levels of abstraction, by simply closing the loop with system verification. Productivity will increase by definition from the potential reduction in silicon spins - but so will design integrity.
A. The Calibre xRC flow provides rapid turnaround for extraction runs. It also gives the designer the ability to focus on critical nets on the design, minimizing the amount of data an extraction run has to process during the design iteration cycle. So its performance and accuracy, combined with its database design management features, gets results back more quickly to designers, reduces design change iteration times, and minimizes the risks of doing large, complex deep submicron designs.
A. The flow is totally open, with APIs providing procedural access to all databases. For example, the flow accommodates an RC reduction tool and an interconnect delay calculator from Ultima Interconnect Technology, an innovative interconnect physical analysis company in Cupertino, Calif.
A. Calibre xRC's parasitic extraction engine is pattern-based, which means that the engine fractures nets into pre-defined patterns and uses the characterization of these patterns to determine the parasitics of the entire net. The patterns can be characterized to any level of accuracy without affecting execution time. This approach allows Calibre xRC to generate very accurate results without requiring increased runtimes.
Calibre xRC uses a 3D extraction methodology, but bear in mind that in the end it really doesn't matter if you use a 2D process a 3D process, or something in between. What does matter is the accuracy of the results that the process gives you. A 3D process that only provides 20% accuracy is not as good as a process that provides 10% accuracy. One indication of Calibre xRC's accuracy is that several pure-play fabs use Calibre xRC internally for cell characterization.
A. Although gate-level extraction "stops" at the cell pins, Calibre xRC will take internal gate geometries into account when extracting parasitics. For example, if interconnects pass over a gate, there will be parasitics between the interconnect and the gate geometries in proximity to it. Calibre xRC calculates those parasitics so the accuracy is comparable for gate- and transistor-level extraction.
A. This is typically a customer decision, and we can calibrate our models to all three. Ideally, the reference should be the toleranced data from process variation (obviously nosingle 3-D answer is "right"), and this is where our work with Design for Manufacturability(DFM) technology will further differentiate the Calibre xRC solution. Q. Can you view Calibre xRC extraction results? A. Yes, Calibre xRC results can be viewed with our Results Viewing Environment (RVE). This is a powerful tool that lets you cross-probe between the netlist including parasitics, the layout, and the schematic.
A. GDSII layout database and process technology information are required. The process information can take the form of parasitic data tables, dielectric constants, permitivities et al, or even an existing LPE file from a competitive tool. Q. What are your future plans for Calibre xRC? A. In the product area, we are developing a new engine for full-chip extraction that will provide improved high-speed performance with the accuracy of flat-type extraction. The thrust of further research and development will be towards performance scaling and design optimization. Performance scaling will occur with the parallel processing of multiple FDBs, and design optimization will be a move towards predicting the behavior of interconnect, rather than post-layout analysis of its effects. This will be enabled by the incorporation of Design for Manufacturability technology.