Calibre nmDRC and Calibre nmLVS are the market share leaders in physical verification. Calibre also leads the market with innovative features such as incremental DRC, which ensures you can complete your design rule checking quickly and efficiently, and equation-based design rules, which let designers define continuous, three-dimensional functions that accurately and precisely reflect the complex physical interactions of today's nanometer designs.
Calibre nmLVS™, the industry-leading physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging. View Product Overview
Calibre nmDRC™, the industry-leading for design rule checking provides fast cycle times and innovative design rule capabilities. View Product Overview
Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly... View Product Overview
The Calibre DESIGNrev layout viewer speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS® files. View Product Overview
Calibre® Automatic Waiver provides automated recognition and removal of waived design rule violations during DRC. Calibre Automatic Waivers eliminates costly time and effort from the verification process,... View Product Overview
Features and Benefits
- Supports the open standard TCL/TK macro language for extensive tool customization.
- Accesses data within the GDSII or OASIS® database
- Dramatically reduces time to tape-out with robust revision and iteration loop capabilities
- Allows convenient re-verification of the full design, or only the data that has been modified
- Efficiently automates chip finishing tasks
Complex Issues in Less Time
With integrations to all the major industry physical design creation tools, Calibre's Results Viewing Environment (RVE)™ reduces the time required to debug complex issues like shorts, antennas and density from days or hours to minutes. Together, these and the other benefits of Calibre ensure the fastest cycle time through physical verification to tape out, and ultimately working silicon.
Hyperscaling technology brings superior scalability and lightening fast run times for computationally intense applications. Hyperscaling offers advanced data processing options that provide the fastest single CPU and multi-CPU performance to verify blocks in seconds and full chips in hours. Hyperscaling extends the useful life of existing shared memory processor systems, and fully utilizes single and dual-core processor distributed rack systems. Hyperscaling improves productivity regardless of your technology node.
Foundry Sign-Off Standard
In nanometer technology, physical verification has become a sophisticated, multi-stage process that demands highly integrated approaches to the processing and handling of huge amounts of complex design data. Calibre's adoption as the sign-off standard at all of the top foundries ensures accurate results for first time success tape-outs.
“Design engineers can rely on high-quality Calibre rule files to verify their designs for TSMC silicon. Not only do we put them through TSMCs rigorous double-blind QA procedure, but, because Calibre has been used to verify designs in our production environment for the last 2.5 years, we know that they cover real-world design conditions.”
Genda Hu Vice President of Marketing, TSMC
Physical Verification Resources
“I was using a previous version of Calibre. I had a complex lvs problem that I was having difficulty locating where the problem was. A Mentor AE recommended I upgrade to the latest version which had lots of improvements in the GUI and reporting of errors. The new Calibre RVE/LVS took me right to the coordinates of the violating instance, and I was able to see the short right away. And it told me exactly which node it was shorted to. I would certainly encourage Calibre users to look into upgrading to the latest release of the software.”
Brent Lickiss, Layout Manager, Adesto Technologies