Calibre's physical verification capabilities are the industry standard for accuracy, reliability, and performance. Calibre® nmDRC and Calibre nmLVS are the market share leaders in physical verification. Calibre also leads the market with innovative features such as incremental DRC, which ensures you can complete your design rule checking quickly and efficiently, and equation-based design rules, which let designers define continuous, three-dimensional functions that accurately and precisely reflect the complex physical interactions of today's nanometer designs.
Complex Issues in Less Time
With integrations to all the major industry physical design creation tools, Calibre's Results Viewing Environment (RVE)™ reduces the time required to debug complex issues like shorts, antennas and density from days or hours to minutes. Together, these and the other benefits of Calibre ensure the fastest cycle time through physical verification to tape out, and ultimately working silicon.
Hyperscaling technology brings superior scalability and lightening fast run times for computationally intense applications. Hyperscaling offers advanced data processing options that provide the fastest single CPU and multi-CPU performance to verify blocks in seconds and full chips in hours. Hyperscaling extends the useful life of existing shared memory processor systems, and fully utilizes single and dual-core processor distributed rack systems. Hyperscaling improves productivity regardless of your technology node.
Foundry Sign-Off Standard
In nanometer technology, physical verification has become a sophisticated, multi-stage process that demands highly integrated approaches to the processing and handling of huge amounts of complex design data. Calibre's adoption as the sign-off standard at all of the top foundries ensures accurate results for first time success tape-outs.
Features and Benefits
- Dramatically reduces time to tape-out with robust revision and iteration loop capabilities
- Allows convenient re-verification of the full design, or only the data that has been modified
- Efficiently automates chip finishing tasks
- Supports the open standard TCL/TK macro language for extensive tool customization.
- Accesses data within the GDSII or OASIS® database
Physical Verification Products
Calibre nmLVS™, the industry-leading physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.
Calibre nmDRC™, the industry-leading for design rule checking provides fast cycle times and innovative design rule capabilities.
The Calibre Interactive™ invocation GUI provides users with fast and easy access to the Calibre® tool suite, enabling designers to perform physical verification and parasitic extraction from within their familiar IC design environment.
Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly in the user’s own design environment.
The Calibre DESIGNrev layout viewer speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS® files.
Calibre Pattern Matching replaces text-based design rule checks with a visual geometry that ensures a precise and accurate implementation of the design specification.
Calibre Automatic Waiver provides automated recognition and removal of waived design rule violations during DRC. Calibre Automatic Waivers eliminates costly time and effort from the verification process, and ensures accurate processing of all waiver information on every DRC run.
Calibre RealTime enables on-demand Calibre sign-off design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.