Calibre RVE

Physical design is a highly iterative process, requiring numerous debug and re-verification cycles. For large deep submicron designs, the total time spent in debug can dramatically impact time to manufacturing. Calibre RVE specifically addresses this problem by identifying design errors instantly in the user’s own design environment. It easily integrates into popular layout environments. With Calibre RVE, designers gain a tool that is easy to use and the information they need to quickly repair errors.

Features and Benefits

  • Seamless automated integration with popular design environments preserves the investment in EDA tools
  • Quick, intuitive debugging in cell/block and full-chip designs reduce debug time and iterations
  • Flexible, customizable interface allows quick, easy selection and sorting of results.
  • Cross probe results between layout, schematic, source netlist, layout netlist and Calibre LVS result files.
  • View all parasitics generated by Calibre xRC in the Parasitic Browsing window to see extracted values.
  • Locates and visualizes DFM recommended rules, working with Calibre DFM tools
  • Automated short isolation debugging makes even the most complex power ground short simple to fix.
  • Mark Calibre DRC errors as fixed or waived for subsequent runs.
  • Fast and intuitive hierarchical SPICE browser for source and layout netlists.

Datasheet

Toolbox