Block-Level Physical Design & Verification
| Block-level design and verification is a critical step in the construction of mixed-signal designs. At this point in the design flow, digital content, analog content, third-party IP from various sources, and mixed-signal content all need to be developed and verified with a tightly integrated set of tools. | |
| For custom and mixed-signal blocks, IC Station provides a complete physical layout and chip assembly environment integrated on the same database. A full featured layout editor, Nanometer Device Generators, Interactive and Automatic Routers are all built into IC Station. | |
Inline integration with Calibre allows the designer to perform parastic extraction, physical verification and DFM-related operations for the block on-the-fly.
- Olympus SoC
The Olympus-SoC solution delivers innovative technologies for 65 and 45 nm processes. It provides the next-generation place and route system that concurrently addresses variations in lithography, process corners, and design modes. Integral to Olympus-SoC is Mentor’s detailed routing architecture which embeds variation-aware timing, optimization and litho-modeling to address optical proximity correction (OPC) and resolution enhancement technology (RET) effects early in the design cycle ensuring faster timing closure for complex process rules. It is capable of simultaneously solving for dozens of different process corners and design modes, ensuring an optimized chip without unnecessary guard banding.
- Pinnacle
The Pinnacle suite provides the fastest and the best design for variability implementation solution for the biggest chips. Built on revolutionary platform architecture Pinnacle delivers the best performance Design for Variability (DFV) engine, handles extremely large designs, and plugs seamlessly into existing design flows. Rapid Physical Feasibility features help engineers in the early design phase to refine and finalize the floor plan and respond to complex design constraints.
- Calibre nmDRC
The industry standard for design rule checking.
- Calibre nmLVS
Industry standard physical verification tool for layout versus schematic.
- Calibre xRC
Calibre xRC offers AMS SoC designers a single parasitic extraction solution that is independent of design style or flow.
- Calibre xL
Full-chip, high-performance parasitic inductance extraction for analog, RF and custom digital nanometer designs
- Calibre LFD: Litho-Friendly Design
Captures manufacturing process variability in the design flow for "LFD clean" sign-off
- Calibre YieldAnalyzer
Integrated suite of analysis tools to reduce variability in design-related yield loss
- Calibre YieldEnhancer
Layout modification platform to automate design yield enhancement
- IC Station SDL
The IC Station® Tool Suite provides the physical layout component of the Mentor Graphics full custom IC design flow. This suite includes application bundles for editing, schematic-driven layout, and top-level floor planning/routing.
- Calibre RVE
Calibre RVE gives designers a tool that is easy to use and gives the information they need to quickly repair errors.
- Calibre Interactive
This interface provide users with the capabililty to access data in industry standard formats (GDS, spice netlists) from the SVDB directory after a Calibre LVS-H run
Featured Events
Meeting the Critical Challenges of IC Implementation
Learn about the evolution of Mentor's comprehensive Design-to-Silicon IC implementation solution.
AAA and Advanced DFM—Collaboration for Success
Design-for-Manufacturing (DFM) requires a close working relationship between a foundry and its EDA partners to ensure that customers can create competitive designs with the highest possible yield.
Approaching Yield in the Nanometer Age: The Framework for an Extensible DFM Methodology
This online tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like.
Calibre Design-to-Silicon Platform Workshop
Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon platform, a comprehensive suite of tools designed to address the complex hand-off between design and manufacturing.
IC Device and Interconnect Extraction for Analysis
This online seminar covers current IC device and interconnect modeling practices and techniques for analysis in the analog/RF (cell and block), digital (full chip) and on-chip memory domains as well as future trends in IC physical modeling.
