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Electronic System Level Design
System Debug
Vista
System Analysis
System Architect
System Integration
Visual Elite
High Level Synthesis
Catapult Synthesis
Catapult Library Builder
Platform-Based Design
Platform Express Professional
Platform Express Integrator's Kit
Platform Express Client
Embedded Systems
Development Tools
EDGE IDE
EDGE Debugger
EDGE Profiler
EDGE and Microtec C/C++ Compilers
EDGE MAJIC JTAG
Operating System
Nucleus Kernel
Nucleus Networking
Nucleus GUI
Nucleus File System
Nucleus USB
Nucleus Bus Support
Nucleus Security
Application Platform
Inflexion Platform UI
Intellectual Property
USB
USB 2.0 OTG (On-The-Go)
USB 2.0 High/Full-Speed Function
High-Speed USB 2.0 PHY
Full-Speed USB 2.0 PHY
USB Software Stack
USB Subsystem
Ethernet
10/100 Platform
10/100/1000 Platform
10-Gigabit
PCI Express
PCI to AMBA 2 AHB Bridge
PCI to AMBA 3 AXI Bridge
PCIe 1.1 Controller Family
Storage
Serial ATA
Serial ATA 1.5/3.0 Gbps PHY
Parallel ATA
PCMCIA
Peripheral
IP Interface
Processor
Mixed Signal
Full-Speed USB 2.0 PHY
High-Speed USB 2.0 PHY
Serial ATA 1.5/3.0 Gbps PHY
IC Nanometer Design
Custom Design & Simulation
Design Architect IC
ADiT
Eldo
Eldo RF
Digital Design & Simulation
Mixed Signal Circuit Simulation
ADVance MS
ADVance MS RF
Block-Level Physical Design & Verification
Olympus-SoC
Pinnacle
Calibre nmDRC
Calibre LVS
Calibre xRC
Calibre xL
Calibre LFD: Litho-Friendly Design
Calibre YieldAnalyzer
Calibre YieldEnhancer
IC Station SDL
Calibre RVE
Calibre Interactive
Chip-Level Floorplan & Place & Route
Olympus-SoC
Pinnacle
Calibre DESIGNrev
IC Station SDL
Layout Verification
Olympus-SoC
Pinnacle
Calibre nmDRC
Calibre LVS
Calibre YieldAnalyzer
Calibre YieldEnhancer
Calibre RVE
Calibre Interactive
Full-Chip Parasitic Extraction
Calibre xRC
Calibre xL
Calibre RVE
Calibre Interactive
Mask Synthesis (RET & Mask Preparation)
Calibre nmOPC
Calibre OPCverify
Calibre LFD: Litho-Friendly Design
Calibre RET (OPC and PSM)
Calibre MDP
Calibre nmDRC
Chip Manufacturing & Test
Scalable Verification
Verification Components
Equivalence Checking
FormalPro
Assertion-Based Verification
Questa AFV (Advanced Functional Verification)
Questa SV (SystemVerilog)
0-In Formal Verification
0-In® Clock-Domain Crossing (CDC)
0-In® CheckerWare® Compiler
Testbench Automation
Questa AFV (Advanced Functional Verification)
Questa SV (SystemVerilog)
inFact (Intelligent Testbench Automation)
Questa Codelink
Coverage-Driven Verification
Questa AFV (Advanced Functional Verification)
Questa SV (SystemVerilog)
0-In® Assertion Synthesis
0-In Formal Verification
0-In® CheckerWare®
Digital Simulation
ModelSim® SE
ModelSim® LE
ModelSim® PE
Analog/Mixed-Signal Simulation
ADVance MS
ADVance MS RF
Hardware/Software Co-Verification
Seamless
Seamless FPGA
Hardware-Assisted Verification
Veloce
TestBench XPress (TBX)
iSolve Solutions
VStationPRO
PCB Systems
System Design
I/O Designer
DxDesigner
Constraint Editor System
RF Design
Board Station
System Design
I/O Designer
Board Architect
Design Architect
Constraint Editor System
RF Design
Analysis & Verification
HyperLynx
ICX / TAU
Quiet Expert
AccuSim II
Physical Design
Topology Router
TeamPCB
Board Station RE
Board Station XE
Xtreme Design
Automation
FabLink XE Pro
RF Design
Data Management
DMS
Manufacturing
CAMCAD Professional
visECAD
CAMCAD Data Suite
CAMCAD Test Suite
eSight DFM
BOM Explorer
Data Exchange
CAMDOCS
Expedition Enterprise
System Design
DxDesigner
I/O Designer
Constraint Editor System
RF Design
Analysis & Verification
HyperLynx
HyperLynx Analog
ICX / TAU
Quiet Expert
Physical Design
Expedition PCB
Topology Router
TeamPCB
Xtreme Design
FabLink XE
Automation
RF Design
Data Management
DMS
Library Manager
Manufacturing
CAMCAD Professional
visECAD
CAMCAD Data Suite
CAMCAD Test Suite
eSight DFM
BOM Explorer
Data Exchange
CAMDOCS
PADS
System Design
PADS Logic
DxDesigner
PADS I/O Designer
Analysis & Verification
HyperLynx
HyperLynx Analog
Physical Design
PADS Layout
PADS Router
PADS AutoRouter
PADS High-speed Routing
PADS Suites
Manufacturing
CAMCAD Professional
visECAD
CAMCAD Data Suite
CAMCAD Test Suite
eSight DFM
BOM Explorer
Data Exchange
CAMDOCS
FPGA/PLD
Design Creation
HDL Designer
HDL Author
HDL Detective
Simulation
ModelSim® SE
ModelSim PE
Synthesis
Precision RTL
Precision RTL Plus
Precision Physical
LeonardoSpectrum
Requirements Tracking
ReqTracer
Design-For-Test (DFT)
ATPG & Compression
TestKompress
FastScan
DFTAdvisor
FlexTest
Memory Test
MBISTArchitect
MacroTest
Boundary Scan
BSDArchitect
Logic BIST
LBISTArchitect
Yield Learning and Diagnosis
YieldAssist
System Modeling
SystemVision
BridgePoint UML Suite
BridgePoint Builder
BridgePoint Model Compiler
BridgePoint Verifier
Electrical System Design and Harness Engineering
Electrical Design
Capital Logic
Capital Integrator
Capital Ground Design
Capital CWS
Capital Component Sizer
Simulation & Analysis
Capital SimWiring
Capital SimTransient
Capital SimSystem
Capital SimScript
Capital SimStress
Capital SimProve
Capital SimCertify
Design Data Management
Capital Manager
Engineering & Manufacturing
Capital HarnessXC
Capital Engineer
Capital Modular
Capital Labor & Material Cost Analyzer
Capital Factory - Bridges
Capital Harness - OEM Modules
Capital Factory - Formboard
Enterprise Integration
Capital Autoloader
Capital Integration Server
Bridges for CHS
Logical Systems Capture
Capital Capture
Views and Documentation
Capital AVAssist Integrator
Capital AVAssist Logic
Capital AVAssist Blocks
Capital AVAssist Filtering
Vehicle Network Design
Network Design
Volcano LIN Network Architect (LNA)
Volcano Network Architect (VNA)
In-Vehicle Software
Volcano Target Package (VTP) for CAN & LIN
LIN Target Package (LTP)
Bootloader (BL)
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