Silicon proven 10-Gigabit Ethernet solution since 2002 in over 6 different processes
Block based “Lego” platform provides optimized functionality and gate counts
Provided as reusable technology independent Verilog source code
Low gate count asymmetric (32-bit Transmit data and 64-bit Receive data) data path option or traditional symmetric (64-bit Transmit and Receive data paths) data path version
Support provided for XGMII, XGXS (XAUI), and XSBI interfaces
User configurable Transmit and Receive FIFOs (optional)
Support for complete, FPGA based, layer 2 subsystem
