Mentor.com :: Intellectual Property Resources

Success Story:Ethernet IP Enables Wintegra to Launch a Powerful New Line of Next-Generation WinPath Devices

Thu, 04 Mar 2010 18:33:00 GMT

Wintegra develops a highly integrated, access packet network processors for its WinPath product line utilizing the Mentor Graphics 10/100/1000 Mbps Ethernet MAC IP.

Success Story:Mentor Graphics and Kawasaki Microelectronics Team Up to Make Communications IP Cores a Cornerstone of Custom ASIC Development

Thu, 04 Mar 2010 18:33:00 GMT

Kawasaki Microelectronics turns to the Mentor Graphics® Intellectual Property division for reliable, proven, and preverified standards-based IP cores.

Success Story:Nethra Imaging successfully launches a new line of NI-20x0 image processors with the help of Mentor Graphics I2C IPblock

Thu, 04 Mar 2010 18:33:00 GMT

As Nethra’s first product entry, the NI-20x0 family of SoC solutions brings the image quality of film to the mobile handset.

Success Story:Successful launch of TranSwitch EtherMap leverages Mentor Graphics Ethernet IP

Thu, 04 Mar 2010 18:33:00 GMT

TranSwitch develops highly integrated communication semiconductors for Ethernet switching, controllers, SONET/SDH transport & switching, and broadband access.

White Paper:The Integrated IP Subsystem: A Converging SoC Solution

Mon, 26 Mar 2007 17:05:54 GMT

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a device that plays, stores, captures, and sends data 24/7 - whenever and wherever a user wants. Such flexible functionality requires hundreds, even thousands of embedded systems and subsystems to perform invisible work when called upon. With so much responsibility resting on these subsystems, the time has come for the industry to re-evaluate various IP design strategies and methodologies.

Product Demo:USB Subsystem IP

Mon, 01 Jan 2007 08:00:00 GMT

Save time, reduce risk and get to market faster by using Subsystem level IP from Mentor Graphics. View the presentation above to see how USB Subsystem IP can help manage your complex IC designs by using a combination of silicon-proven hardware and software IP that is fully integrated and verified into a spec-compliant USB subsystem.

Product Demo:IP Subsystem Video

Wed, 22 Mar 2006 23:02:52 GMT

USB Subsystem IP can help manage your complex IC designs by using a combination of silicon-proven hardware and software IP that is fully integrated and verified into a spec-compliant USB subsystem.

White Paper:The Evolution in Disk-Drive Storage: How Consumer Electronic Storage Devices will Drive Future Growth

Wed, 26 Oct 2005 17:46:58 GMT

The new CE-ATAinterface standard for handheld devices and consumer electronic portables is quickly emerging as the most promising storage interface standard today. Replacing SATA, CE-ATA addresses many of the requirements inherent in small, form-factor drives, which include low pin count, low voltage, power efficiency, cost effectiveness, integration efficiency, and of course, the physical size of the hard drive itself.

The disk-drive storage market is at a critical juncture as it moves forward with the adoption of CE-ATA. This paper examines the history of storage interface standards, how the PATA/SATA interface evolved, and more recently how CE-ATApromises to dramatically change the interface storage landscape as we know it.

White Paper:Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis

Fri, 22 Jul 2005 18:19:11 GMT

This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process nodes, low power, high performance, high cost, short time-to-market, standard-based protocols and successful completion of ASICs constitute a set of current hardware designs challenges.

The electronic system level (ESL) transition to higher abstraction, system verification techniques, reconfigurable platforms, seamless hardware/software architectures and structured ASICs comprise some innovative methodical strategies to cross hurdles.

Ptolemy II platform introduces a comprehensive set of features; concurrency, heterogeneity, hierarchical structure, portability, distributed modeling, component-based framework, code generation, openness and others; that supports implementation of the innovative hardware design solutions.

This paper studies advantages of Ptolemy II features adoption from the innovative hardware design process perspective, presents past and current Ptolemy II hardware design efforts status and proposes several future research work topics addressing Ptolemy II and hardware design complete unified platform.

The paper concludes that the current Ptolemy II platform has low entry-barrier for hardware designers; taking into account the new hardware design challenges; and calls for potential contribution from the hardware design community to the proposed research topics addressing an optimized Ptolemy II platform for complex hardware chip designs.

White Paper:Analog IP Migration Using Design Knowledge Extraction

Fri, 27 May 2005 18:06:50 GMT

Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It relies on design knowledge extraction, which renders it very fast compared to full optimization approaches and allows handling of much larger circuits. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then reproduces a new sized design in the target technology with the same performance as the original design. The migration of a Folded-Cascode amplifier, Low Voltage Delta Sigma A/D and a USB Transmitter is presented in this paper to validate the migration engine.