Overview of Calibre PERC
Calibre PERC is a reliability verification platform, providing robust, full chip, sign-off quality checks in an integrated environment. From your first schematic, through SoC assembly, to the final layout, we are able to provide a repeatable, efficient and effective reliability verification platform capable of verifying your most challenging reliability issues.
In the mix signal design, it is required to have different voltages to support each domain on the chip. However, designers have to make sure there is no signal line directly across from one voltage to another...…View Technology Overview
Users who do Calibre PERC debug using Calibre PERC RVE, desire different sorting and grouping criteria for different PERC-checks such as floating-gate, gates tied to supply etc. This video shows how to...…View Technology Overview
Other Related Resources
White Paper: Accurate and efficient low-power and multiple-power domain verification requires both knowledge of the overall system’s power intent and careful tracking of signals crossing these power domains. Calibre...…View White Paper
White Paper: Voltage-aware DRC is an essential component in the reliability assessment of a design. Calibre PERC is the only comprehensive solution capable of verifying both the geometrical and electrical constraints...…View White Paper
White Paper: Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of...…View White Paper