Ultra Low Leakage/Power, High Density, High Speed Memory IPs for Advanced SoCs
Farzad Zarrinfar, General Manager of the Mentor Novelics business unit, explains how Mentor embedded memory IP is optimized for the latest ASIC and SoC designs. Mentor IP provides the lowest leakage and dynamic power combined with highest speed and density to meet advanced SoC requirements. Using the Mentor embedded memory compiler, memory designs can be precisely configured to meet the most stringent application requirements implemented in 180nm to 28nm bulk CMOS processes.
It is easier to visualize the differences between layout databases by having each database open in different windows and compare those side by side. DESIGNrev can help you to synchronize multiple windows,...…View Technology Overview
Many Calibre runs require some sort of processing before or after the Calibre run. You can set up pre- and post-execution triggers in Calibre Interactive to call procedures immediately before and after...…View Technology Overview
DRC HTML reports are a very useful way to share information from a DRC verification run across project design teams but previously there was no quick and convenient way to set this up. Now there is a way...…View Technology Overview
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Training Course: This course will teach you to effectively use Calibre nmDRC and Calibre nmLVS software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with...…View Training course
White Paper: Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known...…View White Paper