Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis

ABSTRACT

This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process nodes, low power, high performance, high cost, short time-to-market, standard-based protocols and successful completion of ASICs constitute a set of current hardware designs challenges.

The electronic system level (ESL) transition to higher abstraction, system verification techniques, reconfigurable platforms, seamless hardware/software architectures and structured ASICs comprise some innovative methodical strategies to cross hurdles.

Ptolemy II platform introduces a comprehensive set of features; concurrency, heterogeneity, hierarchical structure, portability, distributed modeling, component-based framework, code generation, openness and others; that supports implementation of the innovative hardware design solutions.

This paper studies advantages of Ptolemy II features adoption from the innovative hardware design process perspective, presents past and current Ptolemy II hardware design efforts status and proposes several future research work topics addressing Ptolemy II and hardware design complete unified platform.

The paper concludes that the current Ptolemy II platform has low entry-barrier for hardware designers; taking into account the new hardware design challenges; and calls for potential contribution from the hardware design community to the proposed research topics addressing an optimized Ptolemy II platform for complex hardware chip designs.