SoC Verification Based on IP Reuse Methodologies

ABSTRACT

Simulation is the bottleneck for SoCs (system-on-chip) going to millions of gates. Next chip generation will have to pass through lots of validation tests to prove that their functionality meets the requirements of the original specifications. Designers will face the problem of building high-level testbenches, either in C or in RTL, and run through simulation to see the behavior of the design. This could last for weeks and does not fit in the time-to-market environment everyone's trying to reach.

In this vision, IPs are seen as key components of a quick and clean step to these million gates chips. In order to help the designers, and avoid adding another problem layer, these IPs must be fully qualified and fully verified.

This paper will try to present you how IP verification is possible using the emulation process and how it could greatly reduce the time spent on system verification. It will describe the emulation flow from the Inventra soft core package to the testchip and its results applied to the Inventra M80186 IP core, using the Mentor Graphics SimExpress TM emulator. All these developments were focused on the Design Reuse Methodology of Mentor Graphics, based on reusable IPs.