Farzad Zarrinfar, General Manager of the Mentor Novelics business unit, explains how Mentor embedded memory IP is optimized for the latest ASIC and SoC designs. Mentor IP provides the lowest leakage and dynamic power combined with highest speed and density to meet advanced SoC requirements. Using the Mentor embedded memory compiler, memory designs can be precisely configured to meet the most stringent application requirements implemented in 180nm to 28nm bulk CMOS processes.
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High Density, High Speed Memory IPs, Low Power, Ultra low leakage