White Papers
An Approach to Rapid Implementation of Multiple Emerging Broadband Communications Standards
As IC technology approaches 10 million+ gates per chip, it is widely recognized that large portions of new ASIC designs must leverage pre-existing designs in order to avoid unacceptably long development schedules.
Committees and user groups have begun to form to define IP implementation, usage, and delivery standards. Synthesizable IP, or soft IP, is by far the most flexible in terms of providing a path for migration to next. However, to be of use in the fast moving digital communications area, soft IP must also possess functional flexibility to keep up with algorithm advancements and evolving multiple standards.
Parameterization mitigates the main problem with most currently available soft cores - the inability to adjust them so they fit into a specific design. Parameterized IP offers the ability to tailor the functionality and performance of the core over a multitude of applications.
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Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis
This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process nodes, low power, high performance, high cost, short time-to-market, standard-based protocols and successful completion of ASICs constitute a set of current hardware designs challenges.
The electronic system level (ESL) transition to higher abstraction, system verification techniques, reconfigurable platforms, seamless hardware/software architectures and structured ASICs comprise some innovative methodical strategies to cross hurdles.
Ptolemy II platform introduces a comprehensive set of features; concurrency, heterogeneity, hierarchical structure, portability, distributed modeling, component-based framework, code generation, openness and others; that supports implementation of the innovative hardware design solutions.
This paper studies advantages of Ptolemy II features adoption from the innovative hardware design process perspective, presents past and current Ptolemy II hardware design efforts status and proposes several future research work topics addressing Ptolemy II and hardware design complete unified platform.
The paper concludes that the current Ptolemy II platform has low entry-barrier for hardware designers; taking into account the new hardware design challenges; and calls for potential contribution from the hardware design community to the proposed research topics addressing an optimized Ptolemy II platform for complex hardware chip designs.
When does it make sense to design for reuse?
Design Reuse is part of the solution to closing the widening gap between what is possible to implement in Silicon and what is practical to design with current design methodologies and tools. The question that this paper tries to address is how you ensure that you can get a reasonable return on the extra investment, over normal design, that is required to make a design re-useable.
This paper analyses some of the factors that affect the economic success of reusing designs. It is important to realize is that design reuse is a process, which has to be refined in order to improve; it is not a single event or decision that enables a step change in design efficiency.
IP Reuse Creation for System-on-a-Chip Design
The never ending increase of silicon capacity available to system and IC designers, as predicted by Moore's Law, brings on a cyclical crisis in design methodology and engineering productivity generating a ripple effect through the EDA and electronics industries. The System-on-a-Chip era will need more than available silicon to become a reality. A new design methodology roadmap based on IP reuse needs to emerge.
Two of the EDA giants, Synopsys and Mentor Graphics, took the initiative at DAC 1997 to set the pace for the new challenge of System-on-a-Chip design. After more than a year and the publishing of the Reuse Methodology Manual (RMM) that sets the stage for IP Reuse and System-on-a-Chip design, where do we stand? The Reuse Methodology Manual is well perceived and accepted by the design community and represents a stake in the ground towards ensuring rapid creation of reusable designs.
Throughout this tutorial an attempt is made to describe the total SoC design flow based on reusable IP and will also outline some non-trivial issues during this process: effect of available silicon capacity, SoC integration, SoC verification and documentation.
Embedded Software in the SoC World. How HdS Helps to Face the HW and SW Design Challenge
The challenges regarding design flow, design automation and verification cannot be solved looking to the HW aspects of the design alone.
There is a big need for SoC designers to understand both their classical - the HW - world, and the world of Embedded Software as well. Particular attention needs to be paid on questions like:
- How to deal with IP reuse that is composed of HW and SW.
- How does SW affect the design flow.
- How to enable portability across hardware platforms, different application domains, and so forth.
This paper introduces Embedded Software for SoC and EDA designers, and tries to raise their awareness on software issues they are directly impacted by. However, both classical HW designers and Embedded Software designers have a lot to teach each other, therefore mutual understanding is crucial for solving the SoC design challenges
In the last part of this paper, the concept of Hardware Dependent Software (HdS) is introduced, and how HdS can help to solve some of the issues mentioned before.