Technical Publications
PCIe - Sizing Replay Buffer Appropriately and Achieving High Throughput in the Process
PCI Express is the latest generation I/O technology for high performance chip-to-chip interconnect applications. The overall performance of the PCI Express system depends on how quickly the data flows from node to node and how efficiently the data flows from end to end.
This paper describes the conditions that affect the performance in PCI Express and the special role replay buffers play in achieving high performance. Further, how to decide the appropriate size of the replay buffers for your particular needs will also be discussed.
PCIe - A Technology-Laden Communications Interface for the Future
The increasing I/O bandwidth requirement and decreasing real-estate requirements of the end product necessitate the adoption of faster I/O interconnect technology. The latest PCI Express technology is the third generation of the Peripheral Component Interconnect (PCI) standard aimed at driving faster and more scalable transmission rates than PCI and PCI-X.
This paper provides an overview of the PCI Express technology including configuration and applications. Comparisons in terms of protocols between PCIe and PCI/PCI-X are also described.
The Integrated IP Subsystem: A Converging SoC Solution
The Evolution in Disk-Drive Storage: How Consumer Electronic Storage Devices will Drive Future Growth
The new CE-ATAinterface standard for handheld devices and consumer electronic portables is quickly emerging as the most promising storage interface standard today. Replacing SATA, CE-ATA addresses many of the requirements inherent in small, form-factor drives, which include low pin count, low voltage, power efficiency, cost effectiveness, integration efficiency, and of course, the physical size of the hard drive itself.
The disk-drive storage market is at a critical juncture as it moves forward with the adoption of CE-ATA. This paper examines the history of storage interface standards, how the PATA/SATA interface evolved, and more recently how CE-ATApromises to dramatically change the interface storage landscape as we know it.
Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis
This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process nodes, low power, high performance, high cost, short time-to-market, standard-based protocols and successful completion of ASICs constitute a set of current hardware designs challenges.
The electronic system level (ESL) transition to higher abstraction, system verification techniques, reconfigurable platforms, seamless hardware/software architectures and structured ASICs comprise some innovative methodical strategies to cross hurdles.
Ptolemy II platform introduces a comprehensive set of features; concurrency, heterogeneity, hierarchical structure, portability, distributed modeling, component-based framework, code generation, openness and others; that supports implementation of the innovative hardware design solutions.
This paper studies advantages of Ptolemy II features adoption from the innovative hardware design process perspective, presents past and current Ptolemy II hardware design efforts status and proposes several future research work topics addressing Ptolemy II and hardware design complete unified platform.
The paper concludes that the current Ptolemy II platform has low entry-barrier for hardware designers; taking into account the new hardware design challenges; and calls for potential contribution from the hardware design community to the proposed research topics addressing an optimized Ptolemy II platform for complex hardware chip designs.
Analog IP Migration Using Design Knowledge Extraction
Selecting a Quality IP Supplier: The VSIA QIP Metric and More
Intellectual Property Business Models
Intellectual property licensing has numerous roots in various media including the printed word, music, art, machinery, and sports figures (and for that matter, where would be the Nike Swoosh today without IP licensing?). The EDA industry can learn from the successes of modern IP licensing in the software, firmware, hardware, and semiconductor industries. The question is - what IP business models will ensure the success of both the vendor and the customer?
Companies like AT&T, TI, and Microsoft have built successful businesses based on a combination of assessing value for developed and acquired intellectual property and licensing it to other companies which enhance their market valuation and give them opportunities to sell their own value added products. Each of those companies spent many years in developing business that benefit both customers and vendors.
When does it make sense to design for reuse?
Design Reuse is part of the solution to closing the widening gap between what is possible to implement in Silicon and what is practical to design with current design methodologies and tools. The question that this paper tries to address is how you ensure that you can get a reasonable return on the extra investment, over normal design, that is required to make a design re-useable.
This paper analyses some of the factors that affect the economic success of reusing designs. It is important to realize is that design reuse is a process, which has to be refined in order to improve; it is not a single event or decision that enables a step change in design efficiency.
IP Reuse Creation for System-on-a-Chip Design
The never ending increase of silicon capacity available to system and IC designers, as predicted by Moore's Law, brings on a cyclical crisis in design methodology and engineering productivity generating a ripple effect through the EDA and electronics industries. The System-on-a-Chip era will need more than available silicon to become a reality. A new design methodology roadmap based on IP reuse needs to emerge.
Two of the EDA giants, Synopsys and Mentor Graphics, took the initiative at DAC 1997 to set the pace for the new challenge of System-on-a-Chip design. After more than a year and the publishing of the Reuse Methodology Manual (RMM) that sets the stage for IP Reuse and System-on-a-Chip design, where do we stand? The Reuse Methodology Manual is well perceived and accepted by the design community and represents a stake in the ground towards ensuring rapid creation of reusable designs.
Throughout this tutorial an attempt is made to describe the total SoC design flow based on reusable IP and will also outline some non-trivial issues during this process: effect of available silicon capacity, SoC integration, SoC verification and documentation.
An Approach to Rapid Implementation of Multiple Emerging Broadband Communications Standards
As IC technology approaches 10 million+ gates per chip, it is widely recognized that large portions of new ASIC designs must leverage pre-existing designs in order to avoid unacceptably long development schedules.
Committees and user groups have begun to form to define IP implementation, usage, and delivery standards. Synthesizable IP, or soft IP, is by far the most flexible in terms of providing a path for migration to next. However, to be of use in the fast moving digital communications area, soft IP must also possess functional flexibility to keep up with algorithm advancements and evolving multiple standards.
Parameterization mitigates the main problem with most currently available soft cores - the inability to adjust them so they fit into a specific design. Parameterized IP offers the ability to tailor the functionality and performance of the core over a multitude of applications.