White Papers
Latency versus Packet Buffering for Ethernet
As developers integrate the Media Access Controllers (MAC) into their Ethernet design, they must make a choice as to how they want to buffer the data stream. The two most popular options are the use of latency
buffers or the use of packet based buffers. Each type of buffering scheme includes advantages and disadvantages that must be weighed in order to select the most efficient use of system resources. The paper examines how each choice affects the bandwidth requirements needed to handle the data flow, what the restrictions are that the choice places on the system CPU, and how to determine the amount of memory needed to
implement the preferred scheme.
The conclusions identified by the paper discuss the advantages of using a packet based buffer over a latency buffer because of the lower requirements placed on the system CPU in terms of bus allocation and the
transfer of unnecessary data. While a latency buffer provides lower gate counts due to smaller memory sizes, it requires more software intervention and system resources to accomplish the same goals provided by a packet based buffer.
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Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis
This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process nodes, low power, high performance, high cost, short time-to-market, standard-based protocols and successful completion of ASICs constitute a set of current hardware designs challenges.
The electronic system level (ESL) transition to higher abstraction, system verification techniques, reconfigurable platforms, seamless hardware/software architectures and structured ASICs comprise some innovative methodical strategies to cross hurdles.
Ptolemy II platform introduces a comprehensive set of features; concurrency, heterogeneity, hierarchical structure, portability, distributed modeling, component-based framework, code generation, openness and others; that supports implementation of the innovative hardware design solutions.
This paper studies advantages of Ptolemy II features adoption from the innovative hardware design process perspective, presents past and current Ptolemy II hardware design efforts status and proposes several future research work topics addressing Ptolemy II and hardware design complete unified platform.
The paper concludes that the current Ptolemy II platform has low entry-barrier for hardware designers; taking into account the new hardware design challenges; and calls for potential contribution from the hardware design community to the proposed research topics addressing an optimized Ptolemy II platform for complex hardware chip designs.
An Approach to Rapid Implementation of Multiple Emerging Broadband Communications Standards
As IC technology approaches 10 million+ gates per chip, it is widely recognized that large portions of new ASIC designs must leverage pre-existing designs in order to avoid unacceptably long development schedules.
Committees and user groups have begun to form to define IP implementation, usage, and delivery standards. Synthesizable IP, or soft IP, is by far the most flexible in terms of providing a path for migration to next. However, to be of use in the fast moving digital communications area, soft IP must also possess functional flexibility to keep up with algorithm advancements and evolving multiple standards.
Parameterization mitigates the main problem with most currently available soft cores - the inability to adjust them so they fit into a specific design. Parameterized IP offers the ability to tailor the functionality and performance of the core over a multitude of applications.