White Papers
SoC Verification Based on IP Reuse Methodologies
In this vision, IPs are seen as key components of a quick and clean step to these million gates chips. In order to help the designers, and avoid adding another problem layer, these IPs must be fully qualified and fully verified.
This paper will try to present you how IP verification is possible using the emulation process and how it could greatly reduce the time spent on system verification. It will describe the emulation flow from the Inventra soft core package to the testchip and its results applied to the Inventra M80186 IP core, using the Mentor Graphics SimExpress TM emulator. All these developments were focused on the Design Reuse Methodology of Mentor Graphics, based on reusable IPs.
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The Evolution in Disk-Drive Storage: How Consumer Electronic Storage Devices will Drive Future Growth
The new CE-ATAinterface standard for handheld devices and consumer electronic portables is quickly emerging as the most promising storage interface standard today. Replacing SATA, CE-ATA addresses many of the requirements inherent in small, form-factor drives, which include low pin count, low voltage, power efficiency, cost effectiveness, integration efficiency, and of course, the physical size of the hard drive itself.
The disk-drive storage market is at a critical juncture as it moves forward with the adoption of CE-ATA. This paper examines the history of storage interface standards, how the PATA/SATA interface evolved, and more recently how CE-ATApromises to dramatically change the interface storage landscape as we know it.
Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis
This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process nodes, low power, high performance, high cost, short time-to-market, standard-based protocols and successful completion of ASICs constitute a set of current hardware designs challenges.
The electronic system level (ESL) transition to higher abstraction, system verification techniques, reconfigurable platforms, seamless hardware/software architectures and structured ASICs comprise some innovative methodical strategies to cross hurdles.
Ptolemy II platform introduces a comprehensive set of features; concurrency, heterogeneity, hierarchical structure, portability, distributed modeling, component-based framework, code generation, openness and others; that supports implementation of the innovative hardware design solutions.
This paper studies advantages of Ptolemy II features adoption from the innovative hardware design process perspective, presents past and current Ptolemy II hardware design efforts status and proposes several future research work topics addressing Ptolemy II and hardware design complete unified platform.
The paper concludes that the current Ptolemy II platform has low entry-barrier for hardware designers; taking into account the new hardware design challenges; and calls for potential contribution from the hardware design community to the proposed research topics addressing an optimized Ptolemy II platform for complex hardware chip designs.