White Papers

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Ptolemy-Oriented Structural, Reconfigurable, and Heterogeneous Hardware Design, Verification and Synthesis

Posted in: USB IP

This paper investigates the suitability of Ptolemy II platform for current complex hardware systems design, modeling, simulation, verification, synthesis and implementation. Systems complexity, lower process nodes, low power, high performance, high cost, short time-to-market, standard-based protocols and successful completion of ASICs constitute a set of current hardware designs challenges.

The electronic system level (ESL) transition to higher abstraction, system verification techniques, reconfigurable platforms, seamless hardware/software architectures and structured ASICs comprise some innovative methodical strategies to cross hurdles.

Ptolemy II platform introduces a comprehensive set of features; concurrency, heterogeneity, hierarchical structure, portability, distributed modeling, component-based framework, code generation, openness and others; that supports implementation of the innovative hardware design solutions.

This paper studies advantages of Ptolemy II features adoption from the innovative hardware design process perspective, presents past and current Ptolemy II hardware design efforts status and proposes several future research work topics addressing Ptolemy II and hardware design complete unified platform.

The paper concludes that the current Ptolemy II platform has low entry-barrier for hardware designers; taking into account the new hardware design challenges; and calls for potential contribution from the hardware design community to the proposed research topics addressing an optimized Ptolemy II platform for complex hardware chip designs.

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Featured

Analog IP Migration Using Design Knowledge Extraction 

Posted in: USB IP
Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It relies on design knowledge extraction, which renders it very fast compared to full optimization approaches and allows handling of much larger circuits. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then reproduces a new sized design in the target technology with the same performance as the original design. The migration of a Folded-Cascode amplifier, Low Voltage Delta Sigma A/D and a USB Transmitter is presented in this paper to validate the migration engine.
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Embedded Considerations for USB On-The-Go

Posted in: USB IP

The On-the-Go (OTG) Supplement to the USB 2.0 Specification, published in December 2001, opens up a vast range of exciting new functionalities for USB-enabled devices. Traditionally, USB has maintained a rigid host-function network topology with multiple portable devices acting as slaves to the single PC master. USB OTG changes this paradigm with the ability for a function to act, often only temporarily, as a host. Instead of a strictly PC-centric environment, OTG devices can also communicate directly with existing function devices and even other OTG products. Along with opportunity, of course, come risk and complexity. So, what are the inevitable limitations to host functionality in an embedded (non-PC) device? What are the trade-offs that will have to be made in those devices in order to maximize battery life and minimize form factor? Exactly how PC-like should be expect our OTG devices to be and what are the design decisions that device manufacturers need to consider in order to meet the market's expectations?

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