In “What’s black and stuck on a PCB?” I promised I’d get back to writing about FloTHERM.PACK and how it can really help your thermal modelling by helping you build accurate thermal models of chip packages.
Assuming you’ve been using FloTHERM or FloTHERM.PCB without FloTHERM.PACK I guess I first need convince you about why you should bother. To help me do that I’d like to introduce you to the concept of ‘thermal headroom’.
As you’ll see from the image, it also defines a division of responsibility between the component vendor and systems integrator, with the vendor being responsible for providing data to allow the temperature rise inside the package to be predicted for the specific application environment. It’s the systems integrators job to define the thermal environment for the package. So, the systems integrator should build a model of his or her system, and use a thermal model supplied by the vendor to represent the package. This is fair enough, and something the industry has broad agreement on.
The snag is that whereas some vendors not only provide models, they go the extra mile and attempt to demonstrate their parts will work in a customer’s product, many vendors don’t make thermal models routinely available to their customers. This was a problem for systems integrators when the DELPHI project finished over a decade ago, but it’s a bigger problem today.
The reason is that miniaturization has increased package-level heat fluxes, so that the temperature rise in the package is becoming an increasing contribution to the total temperature rise. Hence to be confident there’s enough thermal headroom to ensure the product meets vendor temperature specifications we need to know the temperature rise in the package quite accurately.
OK, so how far out can you be for the temperature rise in the package? Well, if you model the package as a simple conducting block it’s anybody’s guess. I reckon ± 50% is a pretty conservative estimate – it could be much higher. If you use a 2-Resistor model experience shows the error is normally down around ± 20%-30%, so it’s about twice as accurate, and does not have any more computational cost. If you use a DELPHI model, these are normally better than ±10%. Slightly more expensive than a 2-Resistor model, but definitely worth the expense for any thermally important packages.
When it comes to thermally critical packages, I’d recommend you use a detailed model. The reason is that the interaction of the package and its environment can be quite subtle. Many years ago I was looking into the thermal performance of one of the first Pentium CPGA packages in a wind tunnel, which had a heat sink attached. What I found was that heat passed from the package into the heat sink above the die, and then spread much more easily in the heat sink base than it did in the chip package. As a result, toward the edge of the package the heat sink was hotter than the package, so heat was passing back into the package, heating it back up! Reducing the contact area between the package and the heat sink by giving the heat sink base a central pedestal improved the thermal performance and made it possible to reduce the mass of the heat sink by making the base thinner. Cool!
Often heat transfer and fluid flow do things I don’t initially expect. If you have any similar stories I’d love to hear them.
Dr. J, Hampton Court