Thermal headroom is a concept I’ve been pushing for a few years, but I guess many people aren’t familiar with it, so I thought some additional commentary would be appropriate. Here goes:
What I’ve drawn looks pretty simple. Starting from the ambient we can attribute to total temperature rise for some critical IC to a temperature rise in the air, the PCB and/or heat sink, then the temperature rise in the package, and finally in the die to give us the maximum die temperature. This has to be less than the vendor’s specified maximum junction temperature for the part.
Perhaps it’s no surprise that this is an oversimplification.
One of the ways it’s too simple is that it gives the impression that heat flow from the die junction to ambient is somehow one-dimensional. It’s not. Something I learnt years ago is that the range of thermal conductivities from the best conductor to the best insulator is (optimistically) about 2000W/mK to 0.02W/mK – so 5 orders of magnitude at best, and often more like 4 in practice. Compared with electrical conductivity, this range represents the difference between high-doped and low-doped silicon. Heat even transfers through a vacuum by thermal radiation. Consequently there’s no such thing as a good thermal insulator – heat always spreads through a structure in all directions. The best we can do is encourage more of it to go in a particular direction. You’ll see I’ve put ‘PCB / Heat Sink’ as one part of the temperature rise. That’s because even if the package has a heat sink attached, some heat will still enter the PCB, so the PCB still has an influence on the package temperature.
Another way the chart is too simple is that it leaves out some important details. It’s a sad fact of life in the heat transfer business that interfaces present resistances to heat flow. If you want to get heat out of a package by putting a heat sink on it, using a thermal interface material (TIM) will reduce the contact resistance but it won’t eliminate it, plus the TIM itself won’t be wonderful as a heat conductor.
Yet another oversimplification is that it considers only one junction, whereas the system will contain many – and their temperatures are interdependent. I could give you yet another example of how it’s too simple, but I won’t. Let’s talk instead about why the concept is useful.
The important point, if you’re a systems integrator, is that it’s up to you to decide how to split up the temperature rise outside the package. For example, you could make the board more thermally conductive. Increasing the copper content local to the component will reduce its temperature, but forcing more heat into the board increases the average board temperature, and so can make other components hotter. Used upfront, before anything is finalized in either the mechanical or electronic design flows the possibilities are almost endless – fan selection and positioning, vent sizing and positioning, PCB layout, PCB spacing, heat sink selection and design, etc.
The thermal design needs to be good enough – you need enough headroom to have confidence in the design, not more. The thermal engineer’s job is to partition the allowable system temperature rise wisely, meaning at minimal cost. The only way to do that is to experiment with different design solutions; and the only cost effective way to experiment with the design is through thermal simulation with a CFD tool like FloTHERM or FloEFD.
Used upfront in the design, the potential savings from CFD are huge, particularly in volume electronics where a buck saved on a heat sink can really add up ;). Including thermal design from the concept stage makes for a smoother design flow. Use of CFD concurrent with the mechanical and electrical design flows reduces product cost and delivers more reliable products in less time. We have a whitepaper coming out on that shortly, which I’ll be commenting on soon.
If you’re a package vendor, you’d be doing your customers a BIG favour if you offer them thermal models of your packages. That’s something we can help with. Take a look at FloTHERM.PACK. Its wizard-based user interface is designed to make creating package thermal models easy. I’d recommend you read Robin Bornoff’s blog ‘So, you want to predict component temperatures do you?’ for an on-going discussion of package thermal modelling.
Dr. J, Hampton Court