Posts tagged with 'JEDEC'
The JESD51-14 standard was published in November 2010, prepared by the JEDEC JC-15 Committee on Thermal Characterization. It outlines a new process to measure what is the most common IC package thermal metric, Theta_jc. This is the thermal resistance between the die and the package case face. More specifically the face of the package that is to be cooled by an external heatsinking method. Theta_jc … Read More
Well, the Christian world needs to wait a couple of more weeks for Easter to come. But the lent of the semiconductor thermal management community is close to finish - at least after a long period of my silence here - since I am writing a new post again. And the reason is that we are facing a very busy week: for the semiconductor thermal management community the week between 20 and 26 March will be like … Read More
RthJC, reliability testing, SEMI-THERM, Electronics Cooling, AC LED, T3ster, LED thermal testing, LM80 tests, TIM testing, JEDEC, JESD51-14
I guess, many people who had to find the metric known as “theta-JC” have asked themselves the question great many times: how to measure junction-to-case thermal resistance quickly and accurately?
So did my colleagues at MicReD back in 2004/2005 when they had to do contract measurement of over 80 power transistor packages. The usual answer is: read the relevant standard - such as MIL-883 or … Read More
thetaJC, thermal transient testing, Electronics Cooling, JEDEC, dual interface method, RthJC, T3ster, JESD51, junction-to-case thermal resistance
I believe in simulation and its effectiveness. I’ve seen how much money it can save. I’m also not the most patient person on the face of the planet. Therefore, I like simulation because it can give fast answers to rather big questions. But sometimes you need more. Sometimes you also need to measure the real world.
This is especially true in the world of semiconductors. You see heat dissipation in … Read More
Thermal, T3ster, CTM, JEDEC, characteristics, package, Semiconductor, measurement hardware, NXP Semiconductors
I’m just back from a very productive SEMI-THERM Conference where we launched our new FloTHERM IC product. We had meetings with the editors of 5 leading electronics magazines to coincide with the launch, which was made at our vendor presentation during the exhibition at the start of Tuesday afternoon. Well done to all involved! If you want to see what others are saying about FloTHERM IC check out the … Read More
Thermal Design, SEMI-THERM Conference, Thermal Management, DELPHI Model, Electronics Cooling, 2-Resistor Model, JEDEC, JEDEC JC15, FloTHERM IC
If you are involved with semiconductor packaging design, then have I got news for you.
We just announced the availability of FloTHERM IC – a web-based tool that delivers a high level of automation to design tasks associated with full-spectrum thermal characterization and validation.
From what I understand, a typical semiconductor thermal team spends about 60% of their time on standard package thermal … Read More
Semiconductor, ROI, Smart Parts, CFD, BGA Substrates, Thermal Characterization, JEDEC, Package Design, Validation, FloTHERM IC, FloTHERM PACK
Hmmm…
If you’re guessing it’s a chip package, you’re right – got it in one. Well done!
OK, so what type of package is it?
If you’re thinking it’s a silly question as you don’t know anything about the package, other than I’ve told you its black - that was a hint that it’s an encapsulated plastic part by the way - you’d be right.
You’d need me to tell you if it had leads, and if so on how many sides … Read More
JEDEC, Thermal Guideline, CFD, Chip Package, 2-Resistor Model, Thermal Standard, FloTHERM.PACK, IC Packaging, DELPHI Model, Electronics Cooling