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FloTHERM Products

FloTHERM PACK

Automated, simulation-based IC package thermal characterization

Technical Specifications

Fast, Reliable Package Model Generation

Generate thermal models 20X faster than conventional approaches, with only a few clicks required to parametrically specify a package design. Inbuilt design intelligence will make realistic assumptions about unknown package parameters.

Share and Archive State-of-the-Art Thermal Models

Generate state-of-the-art detailed and compact models of your IC components. Share and archive thermal libraries within your organization using our unique workgroup features.

Once defined, detailed 3D thermal IC package models, 2-Resistor or DELPHI compact thermal models can be downloaded in standard .pdml format for use in FloTHERM®, FloTHERM® XT or FloTHERM® PCB.

Network Assembly Support

FloTHERM PACK now fully supports two-resistor and DELPHI compact thermal models in the more advanced Network Assembly SmartPart in FloTHERM.

Enhanced Package Families

With more than 30 IC package families supported, users can parametrically specify a package design with only a few clicks.

Ball Grid Arrays and CSPs

  • Plastic Ball Grid Array (PBGA) – wirebonded; with or without slug
  • PBGA - Flip-Chip, with or without lid, with glob-top option
  • PBGA - Cavity-Down, including SuperBGA™
  • PBGA - Stacked Die (TFBGA)
  • Ceramic Ball Grid Array (CBGA) - Wirebonded
  • CBGA - Flip-Chip, with or without lid
  • Tape Ball Grid Array (TBGA)
  • ChipArray™ also known as Fine Pitch BGA (FPBGA) or FSBGA
  • Board-on-Chip BOC™
  • MicroStar™ BGA
  • MicroBGA™
  • mZ-Ball Stack

Power Packages

  • TO-220; TO-247; TO-252 (DPAK); TO-263 (D2PAK)
  • SOT-23 SOT-89

Leaded SMT

  • Quad Flat No-Lead (QFN) or MLF™
  • Quad Flat Packs of various kinds including MQFP, LQFP, TQFP – both with and without slugs.
  • Small Outline packages such as SOIC, SOP, SSOP
  • Thin Small Outline Package (TSOP) and TSSOP; Conventional and Lead-on-Chip leadframes.
  • Exposed Pad versions of popular QFP and SOIC/TSOP packages
  • Plastic Leaded Chip Carrier (PLCC)

Leaded Through-Hole

  • PDIP
  • CPGA - Cavity Up
  • CPGA - Cavity Down
  • CPGA - Flip Chip

Upload FloTHERM Detailed Models

Models initially created in FloTHERM PACK can be exported as pdml files for import into FloTHERM for modification. Then re-import them back into FloTHERM PACK for subsequent compact model creation.

Solder Ball Array Maps

Solder ball arrays can now be defined in CSV format and uploaded for all BGA packages.

Detailed Trace Representation for Power Packages

For all power, and low pin count QFN packages, traces on the top surface of the test board are now modeled explicitly. This results in much higher accuracy Theta_jb metric predictions compared to the previous assumption of those traces being smeared over the entire board top surface.

 
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