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Quality Control at the Electronic Package and System Levels

Details

Overview

In part 1 of the presentation we will introduce the basics of thermal transient testing and the corresponding structure function creation for the better understanding of the thermal properties of the heat-flow path.

In part 2 we will show real life examples for both component and system level thermal characterization. An approach for thermal measurement based simulation model creation will also be presented.

Over 50% of the failures in electronic systems are caused by either high junction temperatures or high temperature gradients according to a study by the US Air Force. It is therefore essential to make sure at the earliest design stage of a power semiconductor package that the heat is properly removed from the chip. This is also a requirement for the corresponding cooling assemblies at the system level stage.

Heat transfer to the outside world can be improved by better heatsinks, higher air velocities and liquid cooling - if the application allows it. However, the heat has to reach the surface of the package first. The efficiency of this heat transfer depends on the conductivity of the package itself, the interface thermal resistance that is defined as the sum of the thermal resistance of the interface material (TIM) plus the contact resistances.

The intention of this event is to help engineers decide which characterization steps should be carried out to make sure that the lifetime and quality of an electronic product will not diminish due to temperature induced failures.

What You Will Learn

  • Overview of the thermal transient measurement methodology
  • Characterization of temperature sensitive parameters of semiconductor devices
  • On-chip static and transient measurements in a live system
  • The effect of bad thermal management on the lifetime of an electrical system
  • Overview will be given on accelerated reliability tests
  • A possible definition of the failure criteria for the degradation of thermal interface materials
  • A structure-function based evaluation of die attach failures
  • A measurement based compact model creation methodology

About the Presenter

Presenter Image Andras Vass-Varnai

Andras Vass-Varnai obtained his MSc degree in electrical engineering in 2007 at the Budapest University of Technology and Economics. He works as a technical marketing engineer at the MicReD Division at Mentor Graphics since. Beside his work he is also a correspondent Ph.D. student at the Technical University of Budapest. His main topics of interest include thermal management of electric systems, advanced applications of thermal transient testing, characterization of TIM materials and high power semiconductor devices.

Who Should View

  • Quality engineers
  • Engineers interested in reliability issues
  • System designers of electronic systems with high power density
  • Thermal engineers

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