System-in-Package Technologies - The Need for DfX
On-demand Web Seminar
The challenges of combining digital, analogue and RF functions into a single piece of silicon and optimising this for different process technologies has proved difficult and extremely costly. Despite major advances the System-on-Chip (SoC) option will be very costly if it can be achieved at all. System in Package (SiP) provides a complete system in one module that can be processed much like a standard component during board assembly. This web seminar will discuss the challenges for DfManufacturability and DfReliability for SiP and illustrate some of the current research work in this area and the impact of thermo-mechanical simulation tools.
This web seminar discusses the challenges for DfManufacturability and DfReliability for SiP and illustrates some of the recent research work in this area and the impact of thermo-mechanical simulation tools.
The challenges of combining digital, analogue and RF functions into a single piece of silicon and optimizing this for different process technologies has proved difficult and extremely costly. Although major advances are continuing to be made in the semiconductor industry, for highly complex systems containing multi-functional components the System-on-Chip (SoC) option will be very costly if it can be achieved at all.
System in Package (SiP) provides a complete system in one module that can be processed much like a standard component during board assembly. In contrast with System on Chip, SiP modules can be integrated by stacking dies one upon the other, or combining multiple die stacks onto the same substrate, or even embedding die structures into the substrate. According to the ITRS roadmap future higher value systems will combine the latest advances in SoC (More-Moore) with the diversification provided by SiP (More-Than-Moore).
Design for X (X=Manufacturability, Test, Reliability, etc), DfX, methodologies and associated software tools are playing a very important part in SiP product development.
What You Will Learn
- Benefits and drivers behind SiP
- Wafer-level packaging for SiP
- Technology challenges presented by SiP products
- Reliability challenges
- Need for co-design
About the Presenter
Mr. Bailey is a Professor of Computational Mechanics at Greenwich University, London UK.
Who Should View
- Packaging Engineers
- Engineering Managers involved in SiP product development
- Mechanical and Thermal Engineers and those who want to know more about improving SiP product development through analysis
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