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T3Ster Validation of Thermal Models of IC Packages and More



Learn how Thermal Transient Tester (T3Ster) equipment can be used to generate Compact Thermal Models (CTMs) for use in thermal design to improve junction temperature prediction.

Getting hold of chip package CTMs for use in board and system-level thermal analyses can be tricky, as not all vendors provide them. Until now the ability to create thermal models direct from measurements on actual parts has not been possible. T3Ster records the change in die temperature in response to a power step applied to the device. The packaged semiconductor device measured by T3Ster can be any active part, like a discrete diode, BJT, JFET, MOSFET, IGBT, thyristor, a memory module processor, or even a power LED. Data processing of the temperature vs. time response yields reveals the detailed internal structure of the part, analogous to the way X-rays show internal details of the human body, by recording changes in material properties and geometry along the heat flow, resolving the thermal resistances and capacitances of the die, die attach, die pad, substrate, encapsulate etc. all the way to the ambient. The thermal capacitance / thermal resistance map of the junction-to-ambient heat-flow path, is a 1-D dynamic CTM that captures both the steady-state and transient thermal behavior of the package.

DURATION: 57 minutes

What You Will Learn

  • Technology behind the T3Ster hardware
  • How to use measurement data in CFD simulation software
  • Use of T3Ster for component characterization

About the Presenter

Presenter Image Dr. John Parry

Dr. John Parry, CEng. joined Mentor Graphics’ Mechanical Analysis Division (formerly Flomerics) in 1989 as the head of the Customer Services department. After four years, John moved to the Research department and he has been managing the division’s research activities since 1997.

Having published many technical papers over the years, John’s technical contributions include the development of compact thermal models for fans, heat sinks and chip packages. He is also a subject-matter expert in the application of Design of Experiment and optimization techniques.

John serves on several conference committees. He was the General Chair of SEMI-THERM 21 and currently represents the Mechanical Analysis Division in the JEDEC committee on thermal standards.

Who Should View

  • Thermal Engineers
  • IC Packaging Engineers
  • Mechanical Engineers concerned with the thermal design of electronic products
  • Managers wishing to learn how thermal measurements can identify problems and improve thermal design

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