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Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC’s CoWoS Reference Flow

For more information contact

Sonia Harrison
sonia_harrison@mentor.com
Mentor Graphics
503.685.1165

Gene Forte
gene_forte@mentor.com
Mentor Graphics
503.685.1193

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WILSONVILLE, Ore., October 15, 2012—Mentor Graphics Corp. (NASDAQ: MENT) today announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC’s new CoWoS™ (Chip on Wafer on Substrate) Reference Flow.

The TSMC CoWoS Reference Flow addresses 3D IC multi-die integration challenges including management of placement and routing of micro-bumps, probe-pads, through-silicon-vias (TSVs), and C4 bumps, accurate extraction and signal integrity analysis of high-speed interconnects between dies, thermal analysis from chip to package to system, and integrated 3D testing methodology for die-level and stacking-level tests. The CoWoS Reference Flow enables a smooth transition from 2D IC to stacking design with minimal changes to existing design methodology.

Both the Olympus-SoC™ place and route system for digital designs and the Pyxis™ IC Station custom layout product provide support for CoWoS design implementation. The Olympus-SoC product supports probe pad routing including micro bump and C4 bump routing, routing between combo bumps, and combo bump stream out in DEF and GDS formats. Inter-die design rule checks (DRC) and layout versus schematic (LVS) checks are performed during layout construction to help ensure rapid signoff.

The Pyxis IC Station custom layout product provides redistribution layer (RDL) routing and ground plane generation with the ability to do 45 degree angle routes to vias, and specific enhancements for the TSMC flow include improvements to the bump file import process.

The Calibre® 3DSTACK signoff solution maintains standard DRC, LVS, and parasitic extraction (PEX) verification, and introduces new capabilities to verify physical offset, rotation, and scaling at the die interfaces. It also enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation. The Calibre solution creates minimal disruption to existing verification flows while supporting flexible stacking configurations of multiple die, including die based on different technologies or process nodes.

CoWoS technology brings active die significantly closer to each other than previous packaging approaches, resulting in strong die-die thermal interactions that need to be understood and managed. To address this need, Mentor has created an innovative integration between the Calibre platform and the FloTHERM® 3D computational fluid dynamics software, which can be used with TSMC’s Thermal Management Kit to model temperature variation across the CoWoS design.

The Tessent® solution enables 3D IC testing. It helps ensure a lower escape rate of defective die at wafer test to achieve post-packaging yield, and provides a 3D test infrastructure for delivering tests to any die within the stack, as well as for testing TSV interconnects between stacked die. Key features for 3D IC include:

  • Pre-bond testing of TSVs and IOs using contactless wrap
  • Retargeting of embedded compression scan patterns and built-in self-test (BIST) created at the die level to any die in the stack using DFT access infrastructure
  • Test generation for shorts or opens between logic die
  • Test generation for shorts or opens between DRAM and logic die using the memory die’s JEDEC interface
  • Enhanced memory BIST for thorough testing of vendor independent stacked DRAM die

“Mentor Graphics and TSMC are continuing to collaborate to provide the market with an optimum combination of flexibility, ease-of-use, and interoperability that will help make the adoption of 3D IC design techniques successful,” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “We believe that a comprehensive solution that creates minimal disruption to existing flows provides the highest value for our mutual customers.”

“TSMC is extending its 3D IC capabilities to provide designers with more technology choices as they develop new products,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “CoWoS provides a straightforward way to achieve reduced footprint and power for multi-die systems using different nodes or process types, while minimizing complexity and design cycle time. Mentor is providing various elements to the TSMC flow including design cockpits for both digital and custom designers looking to use TSMC’s CoWoS offering.”

Mentor Graphics, Calibre, FloTHERM and Tessent are registered trademarks, and Olympus-SoC and Pyxis are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.

 
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