Chip-package co-design is important for several reasons. Designing a large high power die, e.g. a System-on-Chip (SoC) without considering how to get the heat out is likely to lead to problems later on, resulting in a sub-optimal packaging solution from cost, size, weight and performance perspectives. Historically IC design has considered the die temperature to be uniform. This is no longer a valid assumption in many cases. Heating due to current leakage, which is temperature dependent, is making power dissipation less uniform, and the use of thinner die, now well below 50µm, has reduced the heat spreading capability of the die itself. Both of these effects contribute to greater on-die temperature variation.