When trying to design SERDES signals on board, designers often receive recommendations on placing stitching vias around differential signal vias of a channel. The purpose is to provide continuous return current path when signals switch layers, so that the discontinuity of trace impedance can be minimized.
Because of the increasing board density, the issues designers are facing by following this recommendation … Read More
This tip comes from Bill Tkachuk in CSD.
Do you want to do pin swapping in a PADS Logic/PADS Layout flow? Take a look at Technote 575205 for the easy to follow steps to follow.
Jim
… Read More
Everybody knows you are supposed to turn off your phone and other electronic devices when you are on a plane. You can leave it on during the flight, but it has to be off for takeoff and landing. I like to remind people in case they “forget”. I tend not to make a big deal during takeoff, but landing has me a little more on edge.
The problem is coupled noise. Sure, most modern planes … Read More
Tags: crosstalk, HyperLynx, coupled noise, noise coupling
In the lab, both simultaneous switching noise (SSN) and crosstalk look the same. They appear as unwanted pulses of energy that line up with the (aggressor) signal edges. However, the mode of energy coupling is much different between SSN and crosstalk. In the case of crosstalk, they are lining up with the edges because the signal edges are coupling energy onto the victim signal through electric (and … Read More
Tags: crosstalk v SSN, HyperLynx, crosstalk, simultaneous switching noise, SSN
Crosstalk is everywhere. Really, in a more general sense, noise coupling is everywhere. Usually the method of noise coupling is traditional “crosstalk” – the unwanted transfer of noise from one place to another through coupled electric fields. This most often occurs on PCB designs with dense routing, and on wide parallel busses. Even on newer SERDES busses, however, it is still … Read More
Tags: crosstalk, HyperLynx, connector crosstalk, via coupling, noise coupling, SSN
Here’s another Tip from Yan Killy, Technical Marketing Engineer:
It is a common practice to use vias to shielding high noise traces. It involves using multiple vias connected to a ground net around the entire high noise trace.
The designer can use “Add Via” command after selecting Ground Net and add them one by one. Doing this manually is time consuming, especially when the trace has a lot of … Read More
Tags: PADS, PADS Tips and Tricks
Found a signal integrity problem in the lab? How do you go about fixing it? Well, if it’s a SERDES bus, you can’t do any kind of re-work because it will most likely kill the signal even more. Maybe you can play with some driver strength or pre-emphasis settings. Or is it a slower, parallel bus? Maybe you can re-work in some necessary termination. This is where post-layout SI simulation … Read More
Tags: post-layout, Pre-Layout, HyperLynx, Signal Integrity
Running at 6GHz is actually kind of scary regardless, but especially so with your eyes closed. And I mean that more figuratively than literally. Obviously, if your eye diagrams are closed on your serial links in your design there is cause for fear, but the fear of the unknown can be even greater, especially if you are running at multi-GHz speeds. That is where a complement of pre-layout and post-layout … Read More
Tags: HyperLynx, post-layout, 6GHz, SATA, Signal Integrity, Pre-Layout, SAS
This weeks tip comes from Yan Killy, technical marketing engineer:
Many times you need to route high current traces. Almost always these wide traces have sense lines that are going to control the circuit.
In Design Rules, setup minimum trace width for the high current net. However, when you start routing the sense line, you want this trace to be thinner. With Advanced Rule Set (ARS option) in PADS, … Read More
Tags: PADS
It’s never too late to fix a design problem. Well, maybe if the product is shipping, that might be classified as “too late”. But during the design phase, whether you’ve laid out your board or not, it’s a good time to make sure there are no design issues. When it comes to signal integrity, that means performing pre-layout or post-layout simulations. I think most experts … Read More
Tags: post-layout, Pre-Layout, HyperLynx, Signal Integrity
