2009 Technology Leadership Awards – The results are in!

2009 Technology Leadership Awards – The results are in!

We recently finished our annual Technology Leadership Awards (TLA) contest, and our esteemed panel of PCB industry experts picked another set of incredible designs. Over the next few blogs I’ll tell you about the winners and what made them unique – but if you can’t wait for the results, you can get the basic information from the press release or the TLA home page.

I’d like to start by going over some statistics from this year’s contest, just to give a PCB geek’s perspective on the complexity of designs today.

• Biggest board: 19.3”x14.5” (490×368mm)
• Smallest board: 0.49”x0.42” (12.5×10.6mm)
• Most layers: 32
• Average trace/space: 4/4th (100×100um)
• Most vias: 73847
• Most nets: 13178
• Largest % high-speed nets: 93%
• Most connections: 55982
• Most components: 22236
• Most FPGAs: 48

Managing numbers like that (e.g. for connections or components) is never an easy problem, regardless of how big the board is or how many layers it has. What’s significant is that the board size (X, Y and layers) is shrinking as the functionality increases. Usage of HDI is increasing, but a number of designs are being built with HDI geometries (e.g. 3-4th), but without HDI technology. That inevitably means a major productivity hit for the poor designers who have to route with that density. The answer in part is design re-use – very few designs are started from scratch – many leverage blocks of design data for chip sets or functions from previous designs.

Leveraging advanced technologies

We asked entrants to specify which advanced technologies they utilized for their designs. The results were fairly predictable, although I’d expect bigger numbers for RF and flex given industry trends. HDI usage is steadily increasing – but at the same time note that while a number of people are considering it due to tight densities, they are still avoiding it due to manufacturing or cost concerns.

Advanced technology usage:

• HDI: 44%
• RF/microwave: 17%
• Flip chip: 13%
• Flex/rigid flex: 7%
• Chip on board: 6%
• Buried capacitance: 6%
• Embedded passives: 4%

Design constraints

We also asked entrants to specify the constraints they had to consider during the design process. Not surprisingly, signal integrity and manufacturability ranked very high on people’s lists. This effectively represents the challenges layout designers face – managing  trade-offs between constraints from the front-end (engineering), and the back-end (manufacturing). As an illustration of best-in-class processes, almost all of the TLA winners designed for signal integrity and manufacturability.

Design for…

• Signal integrity: 89%
• Manufacturability: 89%
• Reliability: 69%
• Power integrity: 63%
• Cost: 59%
• Government compliance: 13%

Of interest was the rather large percentage of people designing for power integrity – this is definitely a rapidly rising challenge. There is also a strong correlation between SI and PI – almost all designs that were PI-constrained were also SI-constrained.

There was some variance in constraints by industry, but not as much as in the past. Industries are seeing common drivers (e.g. long gone are the days when mil/aero designers didn’t have to care about time & cost). In addition, the reuse of computer chip sets/functions in different markets has propagated the high-speed constraint sets, helping to make design for SI almost ubiquitous across all markets.

I’ve included a few images of SI-constrained boards that were submitted.

     

In the next installment I’ll discuss a few trends illustrated by TLA entries over the last 15 years.

More Blog Posts