EIGHT (8) KEY HDI DESIGN FEATURES

EIGHT (8) KEY HDI DESIGN FEATURES

Now that I am retired and working on PCB Fabrication Projects here in Taiwan, I have collected some of my HDI design strategies and condensed them down into 8 KEY DESIGN FEATURES.  Let me list them now before I forget them:

                                 I.      Where to place the blind vias

                               II.      BGA Breakout

                              III.      Reduction of the BIG drilled vias (GND/PWR)

                           IV.      Automation of Routing – Incremental execution

                             V.      Horizontal-Vertical microvia routing pair

                           VI.      Finer traces/spaces and vias/pads

                          VII.      BC and decoupling capacitor removal

                        VIII.      Split PWR plane supply with blind-vias

 

Before I explain these 8 design features, let me ask, “What design density are you getting now”?  A ‘high-density’ board usually has between 90 to 140 connections per square inch (that is, the total connections (pins) on both sides of a board divided by the length X width of the board) while and HDI board can have from 130 to 650 ave. connections per sq. inch.  If you look at the inner-layers (I/L) of this board, you see the following:

§         Typical through-hole boards get from 2.6 to 6.8 inches length per square inch area.

§         Users are now reporting getting 15 to 21 inches per square inch routing on HDI layers, a 3X to 4X improvement.

§         Far side HDI routing is 10 to 14 inches per square per layer.

§         This is going from 6-8% routing efficiency to 20-28% routing efficiency.

Blind-vias have historically been placed around the perimeter of devices including BGAs.  This is usually the best place for them until the pin count begins to exceed 200 pins, after that, placing the blind-vias to form channels is a much better strategy to increase density.  This is seen in Figure 1.

 

 

 

 

 

 

 

 

 

 

 

The new technique of “swing-fanout” developed by Charles Pfeil of Mentor Graphics [1] is one of the most important techniques to open up multiple channels for BGA breakout.  We call this “the Boulevard Breakout” because, like a freeway, there is multiple channels opened up to now route the breakout traces.  This alone will reduce the maximum layers by 2 to 4 layers minimum or even more.  This technique is seen in figure 2 and in Charles’s Book. [1] [2]

The third technique is to reduce the number of drill vias on the board.  The easiest way to do that is to consider the stackup.  What are the most numerous vias on a board?  ANS: “The vias to ground.”  So if the ground layers that is typically LAYER-2 were moved to the surface-then you do not need vias to connect the component to ground, just a ‘tie-in’.  This can eliminate MAY large vias and by the same token, “what is the second most numerous vias on a board?”  ANS:  “The vias to power.”  So if power is moved from the center of the board to be LAYER-2, a blind-via can replace the larger TH via.  Again with the larger drilled vias being eliminated.  By eliminating 20% to 40% of the larger drilled TH vias or drilled buried vias, there is now space on the I/L for 2X to 3X more traces.  These alternatives can be seen in Figure 3.

•         Use of Microvias in Place of Through-Holes

 

•         Layer Stackup Changes to Eliminate Drilled Holes

 

•         Using the Blind Vias to Form Channels

 

•         Placing the Blind Vias to Open Up Boulevards

 

 

Significant improvements have been made to PCB auto-routers in the last few years.   Yet, they will never replace a skilled design person that has years of experience.  The problem is ‘getting years of experience’ or ‘having the time to implement your experience’!  This is where your experience came come to your rescue!  Today it is possible to “automate your hand routing skills” using the new ‘flexible’ auto-routers.  By annotating nets by their electrical performance, and ‘incrementally’ routing these selected nets to particular layers in the stack-up, using SI and PI driven routing, you can create the “AUTO” equivalent of precision hand routing.  Like the Figure 4 below, select ‘one’ net and autoroute it, tune it and then do a SI / PI simulation on it.  Capture the performance and save in the “CONSTAINT” part of the design tool.  Now autoroute all the nets in this performance class using the “CONSTRAINT” to guide it and assigning it to specific layers. This is repeated until all the nets are routed.  By storing the ‘Procedure’, the next time it can be used just by calling it back.  This type of automation is needed as board become more complex with more nets and more-fine pitch components.

An important part of ‘No. 4 design strategy’ is the have an adjacent layer-pair for routing that uses only a blind-via for the crossover.  These can be seen in Figure 3 above as the ‘second’ tier of diagrams.  Each Type of HDI has a blind-via for the routing crossover from ‘horizontal’ to ‘vertical’. These structures can be created by skip vias, multiple build-up or sequentially laminated drilled and laminated vias.  This is also a via structure you will want to have because it provides routing of high-speed critical nets using only the cross-over from horizontal to vertical of small low-inductance blind vias.  These are the lowest inductance vias in the board and ideal for the highest-speed nets.  These will also have a very high density because the crossover will be small blind vias, not the larger buried or TH vias.

 

An important part of increasing circuit density on PCBs is using finer traces/spaces along with smaller vias and pads on those vias.  Work closely with your PCB fabricator to utilize the ever-changing circuit fabrication capability within the industry.  Typical ROADMAPS or evolutionary changes in fabrication capability are listed here:

•         Denser Inner Layers (traces/spaces)

–        .004”/.004” to .003”/.004” to .003”/.003”

 

•         Denser Build-up Layer (via / lands)

–        .006” / .014” to .004” / .012” to .004” / .010”

 

•         Smaller Drilled Holes (via / lands)

–        .012” / .024” to .010” / .020” to .008” / .018

With faster rise-time devices and lower power supply voltages, comes the need for lower power distribution networks impedances.  At high frequencies, this can only be achieved by reducing the distance between PWR and GND.  We have called this ‘buried capacitance’ (BC) but ‘distributed capacitance’ might be a better name.  Starting at 0.005” to 0.004” between PWR / GND, there is a lowering of the PDN impedance.  0.003” is the lowest cost FR-4 that can be used, as below 0.003”, the materials start to get very expensive, quickly.  But as they get thinner, and with higher Dk dielectrics, an increasing capacitance is created between the PWR/GND.  Enough that it is practical (and essential) to start to remove SMT decoupling capacitors.  Using the Reference Cited [4], up to 80% of the normal SMT decoupling capacitors can be removed, freeing up additional room for routing and components.

The last technique involves a design feature used primarily in IC design.  That is to use two, orthogonal layers to distribute PWR as a ‘Mesh Structure’ and to place signals between the different voltages.  This can be seen in Figure 5 and the structure is called a ‘Dual Offset Coplanar Stripline w/Separate GND Reference’.  Line widths and dielectric distances are given for the various impedances that are commonly used.  This structure has the advantage of lower crosstalk but more importantly, it provides voltage to all the components from ‘LAYER_2’ and LAYER_N-1’ using only a blind-via.  Again, helping out with ‘Rule No. 3 design strategy’.

With these eight design techniques, you should be able to achieve 3X to 4X routing density while also reducing your overall design time.

 

Good Luck

 

Additional details and illustrations are available from my HDI HANDBOOK. [4]

1.      Pfeil, Charles, “BGA Breakouts & Routing”, Version 1.5, Mentor Graphics-2008, www.mentor.com

2.      Pfeil, Charles, “Routing BGA Fanout Patterns by PCB Region”, Printed Circuit Design & Fab, July 2008 pp. 47-48

3.      Holden, H.T. & Carrier, P., “Power Integrity Effects of High Density Interconnect (HDI)”, DesignCon-2009, Feb. 2009

4.   Holden, Happy, “HDI HANDBOOK”, Version 1.0, pcb007-2009, free PDF download at http://hdihandbook.com

 

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